STM32 general timer introduction-EEWORLD

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The STM32 timer is a powerful module, and the frequency of the timer is also very high. The timer can do some basic timing, and can also do PWM output or input capture functions.

Clock source problem:

There are eight TIMx, of which TIM1 and TIM8 are connected to the APB2 bus, while TIM2-TIM7 are connected to the

On the APB1 bus. TIM1 & TIM8 are called advanced control timers. The APB2 bus where they are located is also better than the APB1 bus. APB2 can work at 72MHz, while the maximum of APB1 is 36MHz.

The timer clock does not come directly from APB1 or APB2, but comes from a frequency multiplier whose input is APB1 or APB2.

The function of this frequency multiplier is explained below using the clocks of timers 2 to 7: when the pre-division coefficient of APB1 is 1, this frequency multiplier does not work, and the clock frequency of the timer is equal to the frequency of APB1; when the pre-division coefficient of APB1 is other values (that is, the pre-division coefficient is 2, 4, 8 or 16), this frequency multiplier works, and the clock frequency of the timer is equal to twice the frequency of APB1.

Assume AHB=36MHz, because the maximum frequency allowed by APB1 is 36MHz, the pre-division coefficient of APB1 can take any value; when the pre-division coefficient = 1, APB1 = 36MHz, the clock frequency of TIM2~7 = 36MHz (the multiplier does not work); when the pre-division coefficient = 2, APB1 = 18MHz, under the action of the multiplier, the clock frequency of TIM2~7 = 36MHz.

Some people may ask, since the clock frequency of TIM2~7 is required to be 36MHz, why not directly use the pre-scaling coefficient of APB1 = 1? The answer is: APB1 not only provides clocks for TIM2~7, but also provides clocks for other peripherals; setting this multiplier can ensure that TIM2~7 can still get a higher clock frequency when other peripherals use a lower clock frequency.

Another example: when AHB=72MHz, the pre-scaling factor of APB1 must be greater than 2, because the maximum frequency of APB1 can only be 36MHz. If the pre-scaling factor of APB1 = 2, then because of this multiplier, TIM2~7 can still get a clock frequency of 72MHz. Being able to use a higher clock frequency undoubtedly improves the resolution of the timer, which is also the original intention of designing this multiplier.

TIM general timer configuration steps:

1. Configure the TIM clock　　

RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);

RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE);

2. Basic configuration of timer

void TIM2_Configuration(void)
{
  TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
   // TIM_OCInitTypeDef TIM_OCInitStructure ;
   TIM_DeInit(TIM2);                             //Reset TIM2 timer


   TIM_TimeBaseStructure.TIM_Period = 5;       // 2.5ms
   TIM_TimeBaseStructure.TIM_Prescaler = 36000;   //Division 36000
   TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV1; //Clock division
   TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; //Counting direction up
   TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);

TIM_ClearFlag(TIM2, TIM_FLAG_Update);

TIM_ITConfig(TIM2, TIM_IT_Update, ENABLE);

TIM_Cmd(TIM2, ENABLE);
}

TIM_Period sets the value of the period of the auto-reload register that is loaded into the activity at the next update event. Its value must be between 0x0000 and 0xFFFF.

TIM_Prescaler sets the prescaler value used as the divisor of the TIMx clock frequency. Its value must be between 0x0000 and 0xFFFF.

The function of TIM_ClockDivision is to make a delay, which is usually used in special occasions, but you don't need to worry about it.

TIM_CounterMode selects the counter mode.

　　　　TIM_CounterMode_Up
　　　　TIM up counting mode
　　　　TIM_CounterMode_Down
　　　　TIM down counting mode
　　　　TIM_CounterMode_CenterAligned1 TIM center alignment mode 1 counting mode
　　　　TIM_CounterMode_CenterAligned2 TIM center alignment mode 2 counting mode
　　　　TIM_CounterMode_CenterAligned3 TIM center alignment mode 3 counting mode

The MCU clock frequency is 72MHz, APB1 is divided by 2 to 36MHz, so TIM2 automatically doubles the frequency to 72MHz, so the timer interrupt frequency is 72000000/36000/5=400Hz

3. Enable timer interrupt TIM_Cmd(TIM2, ENABLE);

4. Configure NVIC.

   NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQChannel;
   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 4;
   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
   NVIC_Init(&NVIC_InitStructure) ;

5. Write interrupt function

void TIM2_IRQHandler(void)

{

......//Interrupt processing

}

STM32 general purpose timer .

[2012-3-5 7:44:00 | By: zhpg009 ]

STM32 has 8 registers, including two advanced timers TIM1 and TIM8, two basic timers TIM6 and TIM7, and four general timers TIM2-TIM5. The timers are completely independent and do not share any resources with each other. They can be operated synchronously together. All TIMx timers are connected internally for timer synchronization or linking. When a timer is in master mode, it can reset, start, stop or provide clock to the counter of another timer in slave mode.

Timer clock:

The counter clock can be provided by the following clock sources:

1: Internal clock (CK_INT)

2: External clock mode 1: External input pin (TIx)

3: External clock mode 2: External trigger input (ETR)

4: Internal trigger input (ITRx): Use one timer as the prescaler of another timer. For example, you can configure a timer Timer1 as the prescaler of another timer Timer2.

The specific selection of these clocks can be set by the relevant bits of the TIMx_SMCR register. The CK_INT clock here is from the APB1 multiplier. Unless the clock division number of APB1 is set to 1, the clock of the general timer TIMx is twice the clock of APB1. When the clock of APB1 is not divided, the clock of the general timer TIMx is equal to the clock of APB1. It should also be noted that the clock of the advanced timer does not come from APB1, but from APB2.

The core of the timer:

When it comes to the core of the timer, there are naturally two things that are indispensable. One is the counting clock (how long it takes to count once), and the other is how many overflows are counted. These two together determine the overflow time.

The count clock of the timer comes from APB1 or APB2 according to the different timers. To put it simply, the count clock is to divide one second into many parts. However, since the bus clock is generally tens of megahertz, the divided APB is also tens of megahertz, so the APB needs to be divided to a lower frequency, which requires setting the pre-dividing register. For example, the current APB1 is 36MHz. The bold paragraph above has already said that unless the clock division number of APB1 is set to 1, the clock of the general timer TIMx is twice the clock of APB1. At this time, the TIMx clock is 72MHz. Therefore, to divide it to 10KHz, the pre-dividing register TIMx_PSC (as shown below) needs to be set to 7199. Why is it 7199 instead of 7200? The following register introduction explains this point: the counter clock CK_CNT is equal to the TIMx clock/(PSC+1), so you only need to set the register value to 7199. Here, the frequency of 10KHz is equivalent to dividing one second into 10,000 parts, that is, 0.0001 seconds, and the timer increments every 0.0001 seconds.

Note: Because PSC is a 16-bit register, the value range is 0-65535.

The counter automatically reloads the register TIMx_PSC, which stores the number of times the counter is to increase (how many times the counter overflows).

Note: Because ARR is also a 16-bit register, the value range is 0-65535.

In this way, these two registers determine the overflow time. Continuing with the above example, if the ARR register value is set to 5000, it means that the timer increases every 0.0001 seconds, for a total of 5000 times, which means it overflows once every 0.5 seconds.

In summary, the timer overflow formula is: Overflow time (seconds) = (ARR*(PSC+1))/ TIMx clock CK_PSC (MHz)

General timer 3 initialization function:

void Timerx_Init(u16 arr,u16 psc)

{

RCC->APB1ENR|=1<<1; //TIM3 clock enable

TIM3->ARR=arr; //Set the counter to automatically reload value

TIM3->PSC=psc; //Prescaler to get the counting clock

//These two registers must be set at the same time to use the interrupt

TIM3->DIER|=1<<0; //Enable update interrupt

TIM3->DIER|=1<<6; //Enable trigger interrupt

TIM3->CR1|=0x01; //Enable timer 3

MY_NVIC_Init(1,3,TIM3_IRQChannel,2); //Preempt 1, subpriority 3, group 2

}

This function is the initialization function of TIM3. The main function enters an infinite loop waiting for the TIM3 overflow interrupt. When the value of TIM3_CNT is equal to the value of TIM3_ARR, a TIM3 update interrupt will be generated. After the interrupt program is executed in the interrupt, TIM3_CNT starts counting from 0 again.

TIMx_CNT register: This register is the timer counter, which stores the number of times the current timer has counted.

The control register 1 (TIMx_CR1) bit 0 is also used above:

When the timer overflows, the 0 position in the status register (TIMx_SR) will be set as an interrupt flag, and should be reset to zero by software after the interrupt program is executed.

Keywords：STM32 Reference address：STM32 general timer introduction

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