LPC2103 learning external interrupt

LPC2103 has three external interrupt sources, namely external interrupt 0 (EINT0), external interrupt 1 (EINT1), and external interrupt 2 (EINT2). In addition, the 10 capture inputs of LPC2103 can also be used as external interrupt inputs. The difference from external interrupts is that they cannot wake up the CPU in power-down mode.

The figure below shows the structure of the external interrupt system of LPC2103. Seeing this structure, the operation of registers can be understood a lot.

The following are 4 registers related to external interrupts

The following is a detailed introduction to the registers, starting with the external interrupt flag register EXINT.

What we need to pay attention to is that when the corresponding interrupt sets the flag bit to 1, we need to write 1 to the corresponding register bit to clear the flag bit. And in the level trigger mode, the flag bit can only be cleared when the pin is in an invalid state. For example, if it is set to high level trigger, we can only clear the flag bit to 0 when the corresponding pin becomes low level. The specific register description is as shown in the figure:

External interrupt wake-up register EXTWAKE.

The bits in the EXTWAKE register allow the corresponding external interrupt to wake up the processor from power-down mode. And it is not necessary to enable the corresponding interrupt in the vectored interrupt controller to implement power-down wake-up. The advantage of this is that it allows external interrupts to wake up the processor but does not generate an interrupt.

The specific register description is as shown below:

External interrupt mode register EXTMODE.

This register is mainly used to select whether the interrupt mode is level triggered or edge triggered. Note that external interrupts can only be generated if the pin used as the EINT function is selected and the corresponding interrupt is enabled through VICIntEnable.

The specific register description is as shown below:

External interrupt polarity register EXTPOLAR

This register is mainly used in conjunction with the above mode register to accurately describe the interrupt signal waveform.

The specific register description is as shown below:

The following figure shows the external interrupt trigger setting

Here are two points to note when setting the external interrupt pin:

1 If you want to generate an external interrupt, in addition to setting the corresponding pin module, you also need to set the VIC module, otherwise the external interrupt can only be reflected in the EXTINT register.

2 If the device enters power-down mode and wakes up through an external interrupt, the software should correctly set the pin external interrupt function.

The following figure shows the relationship between external interrupts and vector interrupt controller (VIC)

As can be seen from the figure, external interrupts 0~2 correspond to VIC channels 14~16 respectively. Among them, VICIntEnable controls the interrupt enable of the channel, and VICIntSelect is used to allocate channel interrupts. When it is 1, the corresponding interrupt is allocated as FIQ, and when it is 0, it is allocated as IRQ.

In addition, when it is assigned to IRQ, the corresponding channel control register VICVectorCntln and address register VICVectAddrn need to be set.

The following two figures show the settings of level interrupt and edge interrupt, taking external interrupt EINT0 as an example.