PIC16F877 A/D Module

The analog-to-digital converter (A/D) module has up to 8 analog input channels. The analog input charges a sample-and-hold capacitor, and the output of the sample-and-hold capacitor is the input to the A/D converter. The A/D converter uses successive approximation to convert this analog level into a digital conversion result, which is a 10-bit digital number. The analog reference voltage (positive and negative power supply voltage) can be selected by software as the device's power supply voltage (AVDD, AVss) or the level on the AN3/VREF+ and AN2/VREF- pins. The A/D converter has the unique feature of being able to operate in sleep mode.

The structural block diagram is as follows:

 

 

Steps:

The ADRESH:ADRESL registers store the 10-bit result of the A/D conversion. When the A/D conversion is complete, the conversion result is loaded into this A/D result register pair, the GO/DONE (ADCON0<2>) bit is cleared, and the A/D interrupt flag ADIF is set to 1. After the A/D module is configured, the channel for A/D conversion must be selected before starting the conversion. The corresponding TRIS bits of the analog input channels must be set to input. The determination of the acquisition time is described in the "A/D acquisition time requirements" section. After this acquisition time has passed, the A/D conversion can begin. Follow the steps below to perform A/D conversion:
1. Configure the A/D module
• Configure the analog pins/reference voltage/digital I/O (ADCON1)
• Select the A/D input channel (ADCON0)
• Select the A/D conversion clock (ADCON0)
• Turn on the A/D conversion module (ADCON0)
2. Set the A/D interrupt when needed
• Clear the ADIF bit
• Set the ADIE bit
• Set the GIE bit
3. Wait for the required acquisition time
4. Start the A/D conversion
• Set GO/DONE (ADCON0)
5. Wait for the A/D conversion to complete. You can determine whether the conversion is complete by one of the following two methods:
• Query whether the GO/DONE bit is cleared or the ADIF bit is set;

• Wait for the interrupt for A/D conversion.
6. Read the A/D result register pair (ADRESH:ADRESL) and clear the ADIF bit if necessary.
7. To perform A/D conversion again, go to step 1 or step 2 as required.
Figure 23-2 shows the A/D conversion sequence and the terminology used. The acquisition time is the time it takes for the holding capacitor of the A/D module to be connected to the external voltage level. This is followed by a conversion time of 12TAD, starting when the GO bit is set to 1. The sum of these two times is the sampling time. A minimum acquisition time should be guaranteed to ensure that the holding capacitor is charged to the appropriate level to achieve the required accuracy for A/D conversion.

 

A/D conversion clock selection   
The A/D conversion time per bit is defined as TAD. Each 10-bit A/D conversion requires 11.5 TADs. The A/D conversion clock can be selected by software. There are four options for TAD:
• 2Tosc
• 8Tosc
• 32Tosc
• A/D module internal RC oscillator

Registers related to A/D: