ARM9 Basic Tutorial Lessen2—Timer

   In the previous I/O control article, when the program needs a delay, we use loop statements to implement it. This method is simple to delay, but not very accurate. When precise delay is required, this method cannot be used. It is generally implemented using a timer. Here, we will introduce the s3c2440 timer.

► Clock source of S3C2440
   Before explaining, let's first introduce the s3c2440 clock system. Generally speaking, the main clock source of the MCU is mainly an external crystal oscillator or an external clock, and the most commonly used is an external crystal oscillator. Under the correct circumstances, the clocks used in the system are all obtained by processing the external clock source. Since the frequency of the external clock source generally cannot meet the high-frequency conditions required by the system, PLL (phase-locked loop) is often required for frequency multiplication. In the s3c2440, there are 2 different PLLs, one is MPLL and the other is UPLL.
   UPLL provides 48MHz for USB. Here, we mainly introduce MPLL. After the external clock source is processed by MPLL, three different system clocks can be obtained: FCLK, HCLK and PCLK.
   ♥ FCLK is the main frequency clock, used for ARM920T core;
   ♥ HCLK is used for AHB bus devices, such as ARM920T, memory control, interrupt control, LCD control, DMA and USB master module;
   ♥ PCLK is used for APB bus devices, such as peripheral devices' watchdog, IIS, I2C, PWM, MMC interface, ADC, UART, GPIO, RTC and SPI.
   These three system clocks (FCLK, HCLK and PCLK) have a certain proportional relationship, which is controlled by the HDIVN bit and PDIVN bit in the register CLKDIVN. Therefore, as long as we know FCLK, we can determine HCLK and PCLK through the control of these two bits.
   How is FCLK obtained? It is obtained through the frequency of the input clock (ie, the external clock source) through a calculation formula (please refer to the data manual for the specific formula). This calculation formula also requires three parameters (MDIV, PDIV, SDIV), and these three parameters are obtained through the configuration of the register MPLLCON.
   Finally, we use the clearest line to draw the clock generation process:
   external clock source → get FCLK through register MPLLCON → get HCLK and PCLK through register CLKDIVN.
   This configuration process has been completed in the startup file. For example, the external crystal oscillator is 12MHz, and after MPLL multiplication, it gets 400MHz FCLK, and the ratio between FCLK, HCLK, and PCLK is 1:4:8, so HCLK is 100MHz and PCLK is 50MHz.

► Timer characteristics of S3C2440
   S3C2440 has 5 16-bit timers, and timers 0~3 have pulse width modulation function (PWM). Timer 4 has no internal timer with output pins. Timer 0 has a dead zone generator for high current devices. S3C2440 timers 0 and 1 share an 8-bit prescaler, and timers 2, 3, and 4 share another 8-bit prescaler. Each timer has a clock divider, which can generate 5 different divided signals.
   Each timer has its own 16-bit down counter driven by the timer clock. When the down counter reaches zero, a timer interrupt request is generated to notify the CPU that the timer operation is complete.
   The features of the S3C2440 timer are as follows:
   ◎ 5 16-bit timers
   ◎ Two 8-bit prescalers and 2 4-bit dividers
   ◎ Programmable task control of output waveform
   ◎ Auto-reload mode or single pulse mode
   ◎ Dead zone generator►

Timer registers of S3C2440
   S3C2440 timer:
   ● Timer configuration register (TCFGn);
   ● Timer control register (TCON);
   ● Timer n count buffer register (TCNTBn), timer n compare buffer register (TCMPBn);
   ● Timer count observation counter.
   For detailed description of the timer registers, please refer to the S3C2440 chip manual.

   ♥ Timer Configuration Register (TCFGn)
   The timer configuration register is used to configure two 8-bit prescaler values. The reset value of this register is 0. The timer output clock frequency is calculated as follows:
   Timer output clock frequency = PCLK / (prescaler value + 1) / prescaler value

   ● TCFG0 configuration register: [0-7] configure the prescaler value of timer 0 and 1; [8-15] configure the prescaler value of timer 2, 3, and 4.
   ● TCFG1 configuration register: [0-3] configure the prescaler value of timer 0; [4-7] configure the prescaler value of timer 1; [8-11] configure the prescaler value of timer 2; [12-15] configure the prescaler value of timer 3; [16-149] configure the prescaler value of timer 4;

   ♥ Timer Control Register (TCON)
   The TCON register is used to control timers 0~4. The reset value of the register is 0.

 

TCON Register	describe
0~3	Control timer 0: Enable [0], Manual update [1], Match output [2], Auto reload [3]
4	Dead zone enable
8~11	Control timer 1: Enable [8], Manual update [9], Match output [10], Auto reload [11]
12~15	Control timer 2: enable [12], manual update [13], match output [14], auto reload [15]
1516~19	Control timer 3: enable [16], manual update [17], match output [18], auto reload [19]
20~22	Control timer 4: enable [20], manual update [21], automatic reload [23]

 

   ♥ Timer n count buffer register (TCNTBn), timer n compare buffer register (TCMPBn)
   The timer count and compare buffer registers are used to cache the timing value given by the user. When the TCON register is configured to enable "manual update" for timer n, the value will be loaded into TCMPn and TCNTn at the next timing start, and the timing will be restarted. For example, the internal structure of timer 0 is shown in the figure:

   TCMP0 and TCNT0 cannot be directly operated on. [page]

   ♥ Timer count observation counter (TCNTOn)
   The timer count observation counter saves the timer counter value (read-only).

► S3C2440 timer operation
   After the timer is started, TCNTn starts to count down by one. When TCNTn is equal to TCMPn, TOUTn reverses and TCNTn continues to decrement. When TCNTn= 0, TOUTn reverses again and triggers an interrupt (the interrupt has been enabled). If TCON is set to auto-load, the value of TNCTn/TCMPNn is reloaded.

   The steps in the figure are as follows:
   1. Enable the automatic reload function. Set TCNTBn to 160 and TCMPBn to 110. Set the manual update bit and configure the inverter bit (on/off). The manual update bit assigns the values ​​of TCNTBn and TCMPBn to the TCNTn and TCMPn registers respectively, and then sets TCNTBn=80 and TCMPBn=40 to determine the next reload value;
   2. Set the start bit, the manual update bit to 0, the manual update is turned off and the automatic reload is turned on, and the timer starts counting down;
   3. When the value of TCNTn is the same as the value of TCMPn, the logic level of TOUTn changes from low to high;
   4. When TCNTn is 0, an interrupt request is generated and the value of TCNTBn is loaded into a temporary register. In the next timer cycle, TCNTn will be reloaded with the value of the temporary register;
   5. In the interrupt service routine, TCNTBn and TCMPBn are set to 80 and 60 respectively for the next cycle;
   6. When the value of TCNTn is the same as the value of TCMPn, the logic level of TOUTn changes from low to high;
   7. When TCNTn is 0, TCNTn is automatically reloaded with the value of TCNTBn and triggers an interrupt request;
   8. In the interrupt service routine, automatic reload and automatic request are set to invalid to stop the timer;
   10. Even if TCNTn is 0, because automatic reload is set to invalid, TCNTn is no longer reloaded and the timer stops;
   11. No other automatic request is generated.

► S3C2440 timer initialization Taking
   timer 0 as an example, the steps to start the timer are as follows:
   1. Set TCMPB0 and TCNTB0 registers;
   2. Set the TCON register and the count value is loaded;
   3. Start the timer;
   4. The counter is reloaded. ► Timer alarm experiment
   ♥ Experimental equipment
   Hardware:  One       PC                                       One
   YX-AIO embedded comprehensive innovation design platform                        One
   ARM9 core board  Software:  Windows operating system, ADS1.2 integrated development environment, H-JTAG download environment ♥ Experimental content Use the timer delay method to control the buzzer alarm on the YX-AIO embedded comprehensive innovation design platform. ♥ Experimental steps ① Use                                      the ARM9_S3C2440 project template to create a project in the ADS development environment, and add the program code to the project; ② Compile, link and generate the target file in the ADS development environment; ③ Connect the JTAG downloader to the YX-AIO embedded comprehensive innovation design platform and power on the platform; ④ Turn on the H-JTAG software to detect the processor and NOR-Flash; ⑤ Use the H-JTAG software to download the target file (.bin) to the YX-AIO embedded comprehensive innovation design platform; ⑥ Reset the platform. Source code: