AVR Notes 3: Detailed explanation and application examples of AVRmega MCU fuse settings

1. Correctly configure the AVR fuse bits

The configuration of AVR fuse bits is a relatively delicate task, and users often overlook its importance or find it difficult to master. The following are some key points and related matters that need to be paid attention to when configuring the AVR fuse bits.

(1) In the AVR device manual, the fuse bit is defined as programmed (Programmed) and unprogrammed (Unprogrammed). "Unprogrammed" means the fuse state is "1" (disabled); "Programmed" means the fuse state is "0" (enabled). Therefore, the process of configuring the fuse bit is actually "configuring the fuse bit to be unprogrammed state "1" or programmed state "0"".

(2) When using programming tool software that allows you to determine the fuse bit status value by checking the box, please first read the software instructions carefully to understand whether "√" means setting the fuse bit status to "0" or "1".

(3) When using the programming download program in CVAVR, special attention should be paid. Since the initial state of most fuse bits is defined as "1" when the CVAVR programming download interface is initially opened, do not use the "all" option in its programming menu options. At this time, the "all" option will configure the fuse bits of the chip according to the initial state definition of the fuse bits, but in fact it is often not the configuration result required by the user. If you want to use the "all" option, you should first use "read->fuse bits" to read the actual state of the fuse bits in the chip, and then use the "all" option.

(4) Before using a new AVR chip, you should first check the configuration of its fuse bits, then configure the fuse bits according to actual needs, and record the status of each fuse bit for filing.

(5) After the AVR chip is encrypted, only the data in the internal Flash and E2PROM of the chip cannot be read. The status of the fuse bits can still be read, but the configuration cannot be modified. The chip erase command clears the data in the Flash and E2PROM, and at the same time configures the status of the two lock bits to "11", which is in an unlocked state. However, the chip erase command does not change the status of other fuse bits.

(6) The correct operation procedure is: when the chip is unlocked, download the running code and data, configure the relevant fuse bits, and finally configure the chip lock bits. After the chip is locked, if the fuse bits are found to be incorrectly configured, the chip erase command must be used to clear the data in the chip and unlock it. Then re-download the running code and data, modify the configuration-related fuse bits, and finally configure the chip lock bits again.

(7) When using ISP serial download programming, the SPIEN fuse bit should be configured to "0". The default state of the SPIEN bit when the chip leaves the factory is "0", indicating that ISP serial download data is allowed. Only when this bit is in the programmed state "0" can ISP download be performed through the SPI port of the AVR. If this bit is configured as unprogrammed "1", ISP serial download data is immediately prohibited. At this time, the SPIEN state can only be reset to "0" through parallel mode or JTAG programming to open ISP. Under normal circumstances, the SPIEN state should be kept at "0". Allowing ISP programming will not affect the I/O function of its pins, as long as the ISP interface and the devices connected in parallel are isolated when designing the hardware circuit, such as using series resistors or circuit breaker jumpers.

(8) When your system does not use the JTAG interface for download programming or real-time online simulation debugging, and the pins of the JTAG interface need to be used as I/O ports, the fuse bit JTAGEN must be set to "1". The JTAGEN state of the chip is "0" by default when it leaves the factory, indicating that the JTAG interface is allowed and the external pins of JTAG cannot be used as I/O ports. When the JTAGEN state is set to "1", the JTAG interface is immediately disabled. At this time, JTAG can only be reset to "0" and JTAG can only be opened through parallel mode or ISP programming.

(9) In general, do not set the fuse to define the RESET pin as I/O (such as setting the ATmega8 fuse RSTDISBL to "0"). This will cause the ISP download programming to be unable to proceed, because before entering the ISP mode programming, the RESET pin needs to be pulled low to put the chip into the reset state first.

(10) When using an AVR chip with an internal RC oscillator, pay special attention to the configuration of the fuse bit CKSEL. Generally, the default state of the CKSEL bit when the chip leaves the factory is to use the internal 1MHz RC oscillator as the system clock source. If you use an external oscillator as the system clock source, do not forget to correctly configure the CKSEL fuse bit first, otherwise the timing of your entire system will be problematic. When your design does not use an external oscillator (or a specific oscillation source) as the system clock source, do not misoperate or mistakenly configure the CKSEL fuse bit to use an external oscillator (or other different types of oscillation sources). Once this happens, the chip cannot be operated using the ISP programming method (because the ISP method requires the chip's system clock to work and generate timing control signals), and the chip looks "broken". At this time, the only way to save it is to remove the chip and use the parallel programming method, or use the JTAG method (if JTAG is allowed and there is a JTAG interface on the target board). Another way to solve the problem is to try to temporarily add different types of oscillation clock signals to the crystal pins of the chip. Once the ISP can operate the chip, immediately configure CKSEL to use the internal 1MHz RC oscillator as the system clock source, and then reconfigure CKSEL correctly according to the actual situation.

(11) When using an AVR chip that supports IAP, if you do not use the BOOTLOADER function, be careful not to set the fuse bit BOOTRST to "0", as it will cause the chip to not start executing the program from 0x0000 of the Flash when it is powered on. The default state of the BOOTRST bit is "1" when the chip leaves the factory. For the configuration of BOOTRST, the design of the BOOTLOADER program, and the application of IAP, please refer to the relevant content in this chapter.

2. Configuration of important fuse bits in AVRmega16 microcontroller

(1) CLKSEL[3:0]: used to select the system clock source.

(2) SPIEN: SPI download enable bit. The default state is "0" to enable.

(3) WDTON: WDT timer always on setting bit. The default value is "1", which means that WDT is prohibited from always on.

(4) EESAVE: Whether to retain the contents in the EEPROM when executing the erase command. The default state is "1", which means that when the on-chip erase command is executed, the contents in the EEPROM and the contents in the Flash are erased together.

(5) BOOTRST: determines the address of the first instruction executed when the chip is powered on. The default state is "1", indicating that execution starts from 0x0000 at startup. If BOOTRST is set to "0", the program will be executed from the (6) starting address of the Bootloader area at startup.

(7) BOOTSZ1 and BOOTSZ0: Determine the size of the Bootloader area and its starting address. The default state is "00", indicating that the Bootloader area is 1024 words in size and the starting address is 0x1C00.

3. Use and configuration of JTAG port

　　On AVRmega16, the 4 JTAG ports use the same pins as the 4 bits in the PC port (TDI/PC5, TDO/PC4, TMS/PC3 and TCK/PC2). If the JTAG port function is used, once the JTAG interface is enabled, PC[5:2] cannot be used as a normal I/O port, which means that the available I/O port lines are reduced.

In AVRmega16, two fuse bits (JTAGEN and OCDEN) and the JTD bit in the MCUCSR register are used to control JTAG. The JTD bit can be changed by program instructions. The following table shows the control of JTAG by the three control bits.

Note: The initial value of the JTD control bit after power-on reset is "0". At the same time, in order to prevent the JTAG port from being accidentally opened or closed, a specific instruction operation sequence is required to set the JTD: the JTD bit must be written twice within 4 clock cycles to set the JTD flag to the desired value.