STM32 study notes ADC

1.   18 channels, can measure 16 external and 2 internal signal sources, can be set to single-side, continuous, scanning, intermittent mode execution

2.   12-bit precision

3.    Scan mode, automatic conversion from channel 0 to channel n

4.   Self-calibration

5.   Configure sampling time by channel

6.   Intermittent mode?

7.Dual   ADC mode?

8.   Power supply requirement 2.4~3.6V

9.   Input range 0~3.6V

2. Functional Description

1.   Channel selection:

     Each ADC module of STM32 can switch to different input channels and perform conversions through the internal analog multiplexer. A series of conversions performed on any number of channels in any order constitutes a group conversion. For example, the conversion can be completed in the following order: channel 3, channel 8, channel 2, channel 2, channel 0, channel 2, channel 2, channel 15.

    There are two ways to divide conversion groups: regular channel group and injection channel group. Usually, a regular channel group can have up to 16 channels, while an injection channel group can have up to 4 channels.

    When performing scan conversion of regular channel groups, the conversion of injection channel groups can be enabled if there are exceptions. Both regular conversion and injection conversion have external trigger options. DMA requests are generated during regular channel conversion, while injection conversion has no DMA request and requires query or interrupt to save the converted data.

    A less appropriate metaphor is that the conversion of the regular channel group is like the normal execution of the program, while the conversion of the injected channel group is like an interrupt handler outside the normal execution of the program. A regular group consists of up to 16 conversions. The regular channels and their conversion order are selected in the ADC_SQRx register. The total number of conversions in the regular group is written to the L[3:0] bits of the ADC_SQR1 register. An
     injected group consists of up to 4 conversions. The injected channels and their conversion order are selected in the ADC_JSQR register. The total number of conversions in the injected group is written to the L[1:0] bits of the ADC_JSQR register.
     If a regular conversion is already running, in order to ensure synchronization after the injected conversion, the regular conversion of all ADCs (master and slave) is stopped and resumed synchronously at the end of the injected conversion, as shown in the figure.

2.   Single conversion mode:

     In single conversion mode, the ADC performs only one conversion.

3.   Continuous conversion mode:

     In continuous conversion mode, another conversion is started as soon as the previous ADC conversion is completed.

4.   Scan mode:

    This mode is used to scan a group of analog channels.

5.   Injection mode management:

(1) Trigger injection. See the reference manual for details.

(2) Automatic injection. If the JAUTO bit is set, the injection group channels are automatically converted after the regular group channels. This can
        be used to convert up to 20 conversion sequences set in the ADC_SQRx and ADC_JSQR registers.
        In this mode, external triggering of the injection channels must be disabled.

6.   Intermittent mode:

(1) Regular Group
        This mode is activated by setting the DISCEN bit in the ADC_CR1 register. It can be used to perform a short sequence of n conversions (n<=8) as part of the conversion sequence selected by the ADC_SQRx register. N is given by the DISCNUM[2:0] bits in the ADC_CR1 register. An external trigger signal can start the next round of n conversions described in the ADC_SQRx register until all conversions in this sequence are completed. The total sequence length is defined by L[3:0] in the ADC_SQR1 register.
       Example:
  n=3, channels to be converted = 0, 1, 2, 3, 6, 7, 9, 10
  First trigger: The sequence of conversions is 0, 1, 2
  Second trigger: The sequence of conversions is 3, 6, 7
  Third trigger: The sequence of conversions is 9, 10 and an EOC event is generated Fourth
  trigger: The sequence of conversions is 0, 1, 2
  Note: When a regular group is converted in discontinuous mode, the conversion sequence does not automatically start from the beginning after it ends. When all subgroups have been converted, the next trigger starts the conversion of the first subgroup. In the above example, the fourth  trigger re-converts channels 0, 1 and 2 of the first subgroup.

(2) Injection group

        This mode is activated by setting the JDISCEN bit in the ADC_CR1 register. After an external trigger event, the sequence selected in the ADC_JSQR register is converted in sequence for this mode.
An external trigger signal can start the conversion of the next channel in the sequence selected by the ADC_JSQR register until all conversions in the sequence are completed. The total sequence length is defined by the JL[1:0] bits in the ADC_JSQR register.
        Example:
n=1, channels to be converted = 1,2,3
1st trigger: channel 1 is converted
2nd trigger: channel 2 is converted
3rd trigger: channel 3 is converted and EOC and JEOC events are generated
4th trigger: channel 1 is converted
Note: 1 When all injected channels are converted, the next trigger starts the conversion of the 1st injected channel. In the above example, the 4th trigger re-converts the 1st injected channel 1.
2 You cannot use the automatic injection and discontinuous mode at the same time. 3 You must avoid setting the discontinuous mode for both regular and injection groups at the same time. The discontinuous mode can only be applied to a group of conversions.

7.   Dual ADC mode

8.   Data alignment
The ALIGN bit in the ADC_CR2 register selects the alignment of the converted data storage. The data can be left-aligned or right-aligned, as shown in Figure 146 and Figure 147.
The data value converted by the injection group channel has the offset defined in the ADC_JOFRx register subtracted, so the result can be a negative value. The SEXT bit is the extended sign value.
For the regular group channel, the offset value does not need to be subtracted, so only 12 bits are valid.
Data right-aligned:
Injection group
SEXT SEXT SEXT SEXT D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Regular group
0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Data left-aligned:

Injection group
SEXT D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0
Rule group
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0

3. Programming and software configuration

1.

   void ADC_Config(void)
{
  ADC_InitTypeDef ADC_InitStructure; //Define ADC initialization structure variables
  ADC_InitStructure.ADC_Mode = ADC_Mode_Independent; //ADC1 and ADC2 work in independent mode
  ADC_InitStructure.ADC_ScanConvMode = ENABLE; //Enable scanning
  ADC_InitStructure.ADC_ContinuousConvMode = ENABLE; //ADC conversion works in continuous mode
  ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None; //Conversion controlled by software
  ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right; //Conversion data is right aligned
  ADC_InitStructure.ADC_NbrOfChannel = 1; //Number of conversion channels is 1
  ADC_Init(ADC1, &ADC_InitStructure); //Initialize ADC
  ADC_RegularChannelConfig(ADC1, ADC_Channel_14, 1, ADC_SampleTime_28Cycles5);
  //ADC1 selects channel 14, rule group sampling order (1~16), sampling time 239.5 cycles
  ADC_DMACmd(ADC1, ENABLE); //Enable ADC1 module DMA
  ADC_Cmd(ADC1, ENABLE); //Enable ADC1
  ADC_ResetCalibration(ADC1); //Reset ADC1 calibration register
  while(ADC_GetResetCalibrationStatus (ADC1)); //Wait for ADC1 calibration reset to complete
  ADC_StartCalibration(ADC1); //Start ADC1 calibration
  while(ADC_GetCalibrationStatus(ADC1)); //Wait for ADC1 calibration to complete
  ADC_SoftwareStartConvCmd(ADC1, ENABLE); //Enable ADC1 software to start conversion
}