LPC2103 GPIO register-EEWORLD

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GPIO port 0 mode select register
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GPIO0M bit0 is the GPIO port 0 mode select. When it is 0, GPIO is accessed through the APB address (Legacy GPIO). When it is 1, high-speed GPIO port 0 is enabled and GPIO is accessed through the on-chip storage area (Fast GPIO).

Pin function select register
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PINSEL0 and PINSEL1

The PINSEL0 and PINSEL1 registers control the function of each pin (see Table 62 and Table 63 of the datasheet). The direction control bit of the IO0DIR register is only valid when the GPIO function of the corresponding pin is enabled. When the pin is in other functions, the CPU automatically configures the pin direction.

PINSEL0 and PINSET1 values	Function	Reset value
00	Main function: as GPIO pin	00
01	First multiplexing function
10	Second multiplexing function
11	The third multiplexing function

32-bit register PINSEL0 corresponds to PIN0.0-PIN0.15; 32-bit register PINSEL0 corresponds to PIN0.16-PIN0.31.

GPIO control register:
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Slow GPIO control register (APB access register)

register	describe	access	Reset value	address
IOPIN	GPIO pin value register. Regardless of the direction of the pin, the current value of the pin can be read in this register	R/W	NA	0xE002 8000 IO0PIN
IOSET	GPIO pin set register. Writing 1 sets the corresponding pin to a high level, and writing low has no effect.	R/W	0x0000 0000	0xE002 8004 IO0SET
IODIR	GPIO pin direction control register. This register controls the direction of each pin independently, and writing 1 sets the corresponding pin to output.	R/W	0x0000 0000	0xE002 8008 IO0DIR
IOCLR	GPIO pin clear register. Writing 1 sets the corresponding pin to a low level, and writing low has no effect.	WO	0x0000 0000	0xE002 800C IO0CLR

Fast GPIO Control Registers (Local Interface Memory Access Registers – Enhanced GPIO Features)

register	describe	access	Reset value	address
FIODIR	Fast GPIO pin direction control register. This register controls the direction of each pin independently, and writing 1 sets the corresponding pin to output.	R/W	0x0000 0000	0x3FFF C000 FIO0DIR
FIOMASK	Fast GPIO pin mask register. Any operation on the fast IO pin is only valid when the corresponding bit of this register is activated (written to 0).	R/W	0x0000 0000	0x3FFF C010 FIO0MASK
FIOPIN	Fast GPIO pin value register.	R/W	NA	0x3FFF C014 FIO0PIN
FIOSET	GPIO pin set register. Writing 1 sets the corresponding pin to a high level, and writing low has no effect.	R/W	0x0000 0000	0x3FFF C018 FIO0SET
FIOCLR	GPIO pin clear register. Writing 1 sets the corresponding pin to a low level, and writing low has no effect.	WO	0x0000 0000	0x3FFF C01C FIO0CLR

The FIODIR/FIOMASK/FIOPIN/FIOSET/FIOCLR registers can be half-word/byte addressed, see P74.

Keywords：LPC2103 GPIO Register Reference address：LPC2103 GPIO register

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