Communication between Dual CPUs in Embedded Power Grid Analyzer

　　Under the current situation of power shortage in my country, it is very important to monitor power to ensure safe use of power. The research and transformation of power grid analyzers has always been a hot topic of current research. If the power grid analyzer uses a DSP, it not only samples and calculates power grid parameters, but is also responsible for the operation of the control part. Since the information required to be processed by the DSP in actual applications may be a lot, the workload is large, which will affect the processing speed of the analyzer and reduce its work efficiency. Therefore, a new generation of power grid analyzer is proposed here, which uses DSP and AVR single-chip microcomputer to form a dual CPU processor platform, and fully utilizes the ability of DSP to process large-capacity data and complex algorithms. And the control ability of the single-chip microcomputer interface. The ATmegal28 single-chip microcomputer is responsible for peripheral circuit control, including switch output alarm and control, monitoring input switch quantity, analog output, communication with the host computer, and timing and storage parameters. The parameters are obtained by sampling and calculation by TMS320F2812 DSP. After the calculation is completed, the DSP transmits the data to the AVR single-chip microcomputer, and the monitored parameters are also pre-set by the user and then transmitted through the DSP.

　　2 SPI Communication

　　According to the system design requirements, the SPI interface data bus is required to realize data transmission between DSP and AVR microcontroller. SPI is a serial bus peripheral interface. Only 4 buses are needed to connect to the peripherals, and SPI is a true synchronization method. The two devices work under the same clock. It is precisely because SPI communication occupies fewer interface lines and has high communication efficiency, and these two DSP and AVR microcontrollers both support SPI interface, so SPI communication is currently a better design solution.

　　Since the data registers of DSP and AVR microcontroller are shift registers, when data is shifted out of one register, data is shifted in at the other end. When 8 bits are shifted, one SPI communication ends. The difference is that the data received and sent by ATmegal28 during the communication process is always in one register SPDR, so there is simultaneous transmission and reception. The DSP's transmit and receive registers are separate, with SPITXBUF for sending data and SPIRXBUF for receiving data. 8 bits of data are shifted from the AVR's SPDR into the DSP's SPIRXBUF, and at the same time, the DSP's SPITXBUF shifts data into the AVR's SPDR. Every time SPDR shifts out 1 bit, it shifts in 1 bit, and the corresponding DSP's SPIRXBUF shifts in 1 bit. SPITXBUF shifts out 1 bit, thus completing a 16-bit circular shift. The SPI connection between DSP and AVR is shown in Figure 1, where XXXX is the chip select signal, which is valid at low level.

　　3 Device Selection

　　3.1 Introduction to TMS320F2812

　　The TMS320F281x series DSP is a digital signal processor launched by TI. This series of processors is a fixed-point digital signal processor based on the TMS320C2xx core. It integrates a variety of advanced peripherals and provides a good platform for the implementation of motor and other motion control applications. The processing speed of TMS320F2812 is 150 MI/s, which can meet the requirements of fast processing of large amounts of data and algorithms.

　　TMS320F2812 has rich peripheral modules: 128K Flash program memory, up to 128K ROM, 2 event manager modules, watchdog timer module (WDT), serial communication interface (SCI), serial peripheral interface (SPI), peripheral interrupt expansion module supports 45 peripheral interrupts.

　　3.2 ATmega128 Introduction

　　AVR microcontroller is an 8-bit, RISC-structured microcontroller. ATmegal28 is the highest-configuration device in AVR, with a performance of up to 16 MI/s/MHz. It integrates: 128K Flash program memory, 4K EEPROM and 4K SRAM. It has 2 serial communication interfaces (USART), 1 8-bit TWI (I2C) bus interface, 1 serial peripheral interface (SPI), 53 general I/O ports, 4 timers and counters, which are sufficient to meet the control functions required by the system design.

　　3.3 74LVC4245 Introduction

　　Since the logic levels of TMS320F2812 and ATmegal28 are different, the logic high level of TMS320F2812 is 3.3 V, while the logic high level of ATmegal28 is 5 V, a level converter needs to be connected. Here, 74LVC4245 is selected. 74LVC4245 is a level converter for connecting 3.3 V and 5 V levels, providing 8 inputs and 8 outputs. The DIR pin of 74LV4245 controls the transmission direction of the signal, and its transmission direction is always set to B to A. Its OE pin controls the device to be enabled or in isolation.

　　4 System Hardware Design

　　Figure 2 is the circuit diagram of the system hardware design. Among them, SCK is the clock signal, which is used to provide clock pulses for SPI, and SS is the chip select signal. When SS is pulled low, SPI is triggered, and communication between DSP and AVR is realized. MOSI is master-out slave-in. For the host, data is output from the MOSI pin; for the slave, data is input from the MOSI pin; and MISO is the opposite, it is the master-slave-out pin. For the host, data is input from the MISO pin, and for the slave, data is output from the MISO pin. The host can also reset the slave through the reset pin under necessary conditions (such as when the host is reset).

　　Since the MISO pin of ATmegal28 is sent outward, which is different from the other four pins, and the direction of 74LVC4245 is B to A, the connection method of this pin is different from the other pins. It needs to pass through a voltage divider resistor and use a diode to clamp its voltage at 3.3 V.

　　5 System Software Design

　　5.1 Communication Protocol

　　To achieve communication between two devices, the protocol for transmitting data must be specified first. According to the requirements, the host should send calculation data and configuration information to the slave, and the slave sends an alarm status and response to the host to inform the sender whether the message is received correctly, as shown in Figure 3.

　　The communication protocol between DSP and AVR microcontroller adopts the internally developed SPI communication protocol. Table 1 lists the three data formats for communication between TMS320F2812 and ATmegal28. The receiver uses the start code to identify the type of frame. The parameter type represents different parameters, such as "0x01" means setting time. For example: 3D 01 0008 0A 0A 00 11 14 00 A2 FC, because 0x3D is the ASCII code of "=", the frame represents a data frame, the parameter type is 0x01, it can be seen that this is a data frame for setting time, the last 2 bits are CRC checksum, the remaining sequence "00 08 0A 0A 00 11 14 00" is the parameter, that is, time, set the time to 17:20:00 on October 10, 2008, and the parameter is 4xN bytes to maintain compatibility with the previous generation of products. When the slave receives and verifies it correctly, it will set the time and return a response frame indicating that it is correct. [page]

　　5.2 SPI Initialization

　　The initialization of TMS320F2812 includes: configuring the I/O port as an interface with SPI special functions, selecting the master and slave, data transfer mode, baud rate and send and receive data length. All settings are implemented by designing the corresponding SPI control registers.

　　The initialization of ATmegal28 is similar to that of TMS320F12812. The difference is that since ATmegal28 is a slave, there is no need to select the baud rate. At the same time, it should be noted that the data transfer mode should be consistent with the host. There are 4 data transfer modes, which are set by setting CPOL and CPHA in the control register, as shown in Table 2.

　　The SPI communication of TMS320F2812 does not use interrupt mode. Because it is the main sender, when ATmegal28 has data to send, it will know through external interrupt. ATmegal28 uses interrupt mode. When data is sent, it enters SPI interrupt and starts receiving data.

　　5.3 DSP Receiving and Sending

　　The following is the program code for DSP to receive data:

　　Among them, SpiaRegs. SPISTS. bit. INT_FLAG is the reception completion flag. When a byte is transmitted, SpiaRegs. SPISTS. bit. INT_FLAG is set to 1. Since the SPI data register of TMS320F2812 is 16 bits, the lower 8 bits are the received data.

　　The following is the program code for sending data of DSP:

　　void DSP_Spi_Write_Byte(Uchar Byte_Out) //Send 1 byte to the SPI bus

　　{ Byte_Out=(Byte_Out<<8)&0xFF00；//High 8 bits are valid when sending while(SpiaRegs．SPISTS．bit．BUFFULL_FLAG=1); //There is data in fFXBUF. It has not been removed yet

　　SpiaRegs. SPIT_XBUF=Byte_Out;

　　}

　　Similarly, when the DSP sends data, it first determines whether the data in the cache has been removed. Once it determines that the data has been removed, it immediately writes the data to be sent into the cache.

　　5.4 AVR Transmission and Reception

　　SPIF is the send completion flag. When the data in SPDR is sent, SPIF is set to 1. At this time, data can be written to SPDR. Note that the AVR microcontroller sends an interrupt signal to the DSP before sending data to the DSP. ATmegal28 receives data in an interrupt mode. The flowchart of the interrupt program is shown in Figure 4.

　　6. Notes

　　(1) After pulling down the chip select signal SS, a delay is required before sending data. Due to the difference in logic levels, a level converter 74LV4245 should be added between TMS320F2812 and ATmegal28. When the host pulls down the chip select signal. Due to the existence of 74LVC4245, the two cannot work immediately and a delay will occur. Therefore, a delay function needs to be added in software programming. Generally speaking, a delay of 1μs is sufficient.

　　(2) When AVR writes data to SPDR, SS is pulled high. Generally speaking, the data transmission between two MCUs will not be only 1 byte. In the design, when the slave sends data to the host, if the chip select signal SS is not pulled high after the host receives the first byte, the slave will not be able to write the data into the register, and the host will not be able to receive the data correctly, which will cause data loss and errors. Therefore, the host must pull C high after receiving each byte. After the slave writes the data, pull SS low, so that the data can be transmitted correctly.

　　7 Conclusion

　　Experiments have proved that SPI communication between TMS320F2812 and ATmegal28 fully meets the system requirements. Because SPI timing is simple, the transmission speed is fast, and the interface lines occupied are few, the system design is simplified. At the same time, the use of dual CPU design system enhances the real-time processing capability of the system, reduces the burden of the main CPU, and improves the performance of the product.