Design of a Single-Chip Computer System Based on 8086 CPU

1 Introduction  

With the development of ultra-large-scale integrated circuit technology, it has become a reality to integrate millions or even hundreds of millions of transistors on a chip. Now, chip manufacturers are taking minimizing area and maximizing functions as their development direction. Deep submicron effect theory and IP core technology are increasingly receiving widespread attention from the theoretical and industrial circles. System chip is an inevitable trend in the current technological development. The development of computers has gone through vacuum tube computers, transistor computers, integrated circuit computers and large-scale integrated circuit computers. Its development has always been to integrate more and more functions in smaller and smaller spaces. It can be predicted that in certain specific fields, the overall trend of the semiconductor manufacturing industry towards integrated single-chip systems will become increasingly obvious.  

The so-called single-chip computer is to integrate the chipset, CPU, memory, graphics card, sound card and network card on the motherboard in the traditional PC case to the maximum extent in a single chip. Compared with traditional PCs, single-chip computers have greatly reduced weight, volume and power consumption, so that system performance will be greatly improved, while bringing a breakthrough reduction in price, which directly promotes the rapid popularization of computers.  

The single-chip computer system built in this paper is based on the standard 8086 CPU, integrating peripheral IPs such as AMBA bus, SDRAM, 8255, ROM, etc., and realizing functional demonstration on the Altera DE2 FPGA development board.  

2 Overview of the development of single-chip computers A  

single-chip computer is a complete computer system. The CPU, memory and input and output interfaces are connected through the bus to form the basic system of a single-chip computer. The system-level design of a single-chip computer is an I/O and peripheral integration process based on the CPU, which is the basic SoC design process.  

In recent years, microprocessor manufacturers such as Intel, AMD and VIA have launched platform strategies to combine microprocessors and chipsets to form a complete solution, and plan to further launch single-chip microprocessors that integrate all chips in the future. Intel has frequently promoted platform strategies and plans to further launch single-chip computers that integrate all chips. It has also established a research and development team of 500 engineers to develop its single-chip computer products, hoping to integrate all 32 chips on the current computer motherboard into a single chip. In the AMD quad-core Opteron processor, four independent CPU cores are integrated into a single silicon chip. Each core has a separate 64KB L1 data cache, 64KB L1 instruction cache and 512KB L2 cache. The four cores share 2MB (or larger) L3 cache. In this way, each CPU core can give full play to its own performance, thereby greatly improving the performance of the entire processor.  

The design of a single-chip computer is a SoC design process based on a certain type of CPU and its peripheral I/O interface. Therefore, choosing which type of CPU to use becomes the primary issue of the design. Considering the design difficulty and engineering progress factors, and considering that the selected CPU must be representative, the standard Intel 8086 CPU was finally selected. The basic structure of a single-chip computer based on 8086 is shown in Figure 1.  


  
3 Design of a single-chip computer system  

The 8086 CPU chip has two working modes, minimum mode and maximum mode. The so-called minimum mode means that there is only one 8086 microprocessor in the system. In this case, all bus control signals are directly generated by the 8086 CPU, and the bus control logic circuit of the system is reduced to a minimum. This mode is suitable for small-scale microcomputer application systems.  

This experiment uses the minimum working mode of 8086 to design a single-chip computer. The so-called single-chip computer system design, in addition to the CPU, ROM, RAM, bus, address latch, data transceiver, and peripheral address decoding circuit, integrates one or more peripheral I/O interfaces to form a complete system. The system structure diagram is shown in Figure 2. The  


  
8086 single-chip computer system designed in this paper integrates a bus that complies with the AMBA protocol, an 8255 general parallel interface, and an SDRAM controller. Here, taking the 8255 general parallel interface as an example, the design of a single-chip computer system containing an 8255 application circuit is introduced. As a peripheral I/O device, 8255 communicates with the 8086 CPU through the AHB bus.  

The RTL level design of a single-chip computer system is a SoC design process. It includes the design of the CPU subsystem, the selection and interface design of the bus, and the interface design of the memory unit.  

3.1 Design of the CPU subsystem  

The CPU subsystem includes the 8086 CPU, data transceiver controller, address latch, and memory decoding circuit.  

When the CPU exchanges with the memory (or I/O port), the CPU must first send out the address signal, and then send out the control signal and transmit the data. Therefore, it is necessary to add an address latch to latch the address first so that the address is stable during the read and write bus cycle.  

The data transceiver controller is equivalent to a bus switch, which is used to control the CPU's data bus to select to send or receive data from the storage unit or I/O port to match the communication timing. The memory  

decoding circuit is the same as the 74LS138 principle, using the address line to generate the chip select signal of the ROM and RAM units. After the CPU is powered on and reset, the address is FFFF0H. First, the program is read from the ROM. The program is an unconditional jump instruction that can make the CPU jump to the address of the RAM. The CPU then reads the program from the SDRAM.  

3.2 Bus selection and design  

The integration of the bus has a very positive significance for reducing the chip area and reducing the fan-out of the bus. The standard 8086 CPU generally adopts the traditional three-bus structure, namely the address bus, data bus, and control bus. Based on this bus architecture, IPs such as 8255, display, keyboard/mouse, and network card can also be expanded.  

3.2.1 Bus protocol selection  

The traditional 8086 series CPU system buses include ISA bus and EISA bus. The ISA bus is a 16-bit system bus with an operating frequency of 8MHz and a data transmission rate of 16MB/s. EISA is an open bus standard with a data width of 32 bits expanded on the basis of the ISA bus. The maximum transmission rate can reach 33MB/s. However, due to the relatively low I/O speed, these two bus technologies have gradually been eliminated. [page]

AMBA has many third-party support and has become one of the widely supported existing interconnection standards in the design of SoC based on the ARM processor core. The 2.0 version of the AMBA standard defines three groups of buses: AHB (AMBA high-performance bus), ASB (AMBA system bus), and APB (AMBA peripheral bus). The interconnection of the AHB bus architecture adopts the traditional shared bus mode with master modules and slave modules, and the interface and interconnection functions are separated, which is of great significance for the interconnection between modules on the chip. Therefore, the bus selected in this paper complies with the basic specifications of the AHB bus transmission, and on this basis, some bus interfaces are added and modified according to the characteristics of the 8086 CPU. The entire design mainly includes two aspects: the matching of the transmission timing of AHB and 8086; the expansion design of the bus interface based on the 8086 CPU. The bus structure diagram is shown in Figure 3.  


  
3.2.2 Matching of transmission timing  

Because the transmission protocols of the AHB bus and the CPU are different, it is necessary to match the timing of the two interfaces to ensure that the CPU and other peripheral IPs can communicate normally through the bus. The relevant interface control signals are shown in Table 1.  


  
The interface module first determines whether the access is to the memory or the I/O device based on the MIO signal. If it is an I/O device, when the READY signal is sampled to be high, it obtains the AHB bus control right and communicates with the peripheral I/O device. The designed state machine is shown in Figure 4.  


  
T1: Determine whether the current CPU needs to access the peripheral I/O based on the MIO signal. If the 8086 processor core accesses the memory unit instead of the device on the AHB bus (that is, MIO is 1), the state machine maintains the T1 state and does not send a bus request signal to the AHB bus (that is, the HBUSREQ signal is set to 0). If MIO is low, it jumps to T2.  

T2: After the state machine enters the T2 state, it sends a bus request signal to the AHB bus (that is, the HBUSREQ signal is set to 1) to request access to the bus from the AHB bus arbiter. At the same time, the READY signal is detected. When the READY signal is detected to be high, the AHB bus arbiter gives the bus access rights to the 8086 processor core, and the state machine enters the T3 state at the next clock rising edge. On the contrary, if READY is always low, it means that the slave device on the AHB bus that the 8086 CPU wants to access is not ready, and the 8086 processor core is required to insert the waiting state. The state machine keeps the T2 state unchanged.  

T3: The CPU communicates with the peripheral IP through the AHB bus until the communication ends and returns to the T1 state.  

The read and write signals of the 8086 processor core are controlled by the READY signal. When the READY signal is high, data can be received and sent, otherwise the read and write signals are maintained. The READY signal is determined by the slave device transmission completion signal HREADYIn on the AHB bus, the AHB bus permission signal HGRANT, and the slave device response signal HRESP. The read and write control signal HWRITE on the bus is generated by the combinational logic. The pseudo code of the generation process is shown in Table 2.  


  
3.2.3 Bus interface expansion  

In addition to the data, address bus, read/write and READY control signals, the 8086 CPU also has interrupt request and response and related port signals of external DMA devices. These signals are not available in the standard AHB bus, so the bus interface needs to be expanded to match the 8086 CPU. The expansion design of the bus interface mainly includes two parts: interrupt processing and DMA data channel. The port signals of the 8086 CPU regarding interrupts and DMA are shown in Table 4. [page]


  
After receiving the interrupt request from the peripheral, the system bus will submit an interrupt request to the CPU. Once the interrupt response is received, the interrupt response signal will be transmitted to the peripheral, and the decoding unit will be modified to select the peripheral to ensure that the interrupt type number can be transmitted to the CPU through the bus during the second interrupt response, so that the CPU can successfully jump to the interrupt service subroutine.  

When executing data transmission, the DMA controller needs to master the control of the AHB bus and send address and control signals to the on-chip memory or other peripherals on the bus, which is equivalent to the master device of AMBA. On the other hand, before the DMA controller starts working, the CPU needs to pre-process it so that it can work according to specific configuration parameters. In this initialization stage, the CPU is the master device on the AHB bus, and the DMA controller is a slave device. Based on this duality of the DMA controller, a dedicated DMA channel is equipped in the bus design to match it: when the CPU works normally,  

the DMA plays the role of a slave device and accepts the initialization of the CPU; using HLDA as an arbitration signal, when the CPU responds to the peripheral DMA request (that is, HLDA is high), it gives up the bus control to the peripheral and uses the DMA data channel to transmit data. The transmission protocol also complies with the AMBA protocol. The status of the bus timing control module is shown in Figure 5.  


  
3.3 Interface design of storage unit  

The memory subsystem includes a RAM and a ROM. The 8086 CPU supports a 20-bit address bus and has a 1M-byte storage space, which is divided into a RAM area and a ROM area. This paper uses the on-chip ROM resources of the development board to be configured in a 16k*16 format as the ROM unit in the memory, and uses the 8M SDRAM on the DE2 development board to be configured in a 256K*16-bit bus format to replace the RAM unit in the memory.  

Among various random access memory devices, SDRAM is a relatively ideal device with its low price, small size, fast speed and large capacity. However, the control logic of SDRAM is relatively complex and has very strict timing requirements, which requires a dedicated controller: to control the initialization, refresh and precharge of SDRAM and basic read and write operations. At the same time, it is necessary to match the read and write timing of the SDRAM controller and the 8086 CPU. The state machine of the specific implementation of this interface is shown in Figure 6.  


  
T1: When RDY is high, first determine whether to perform a read or write operation. At this time, DONE is 0: Read: Set WR=0, RD=1; Write: Set WR=1, RD=0.  

T2: When the DONE signal is high, it indicates that the read/write operation can be performed, and jump to T3.  

T3: The CPU performs read and write operations on the SDRAM through the SDRAM controller.  

T4: When the low-byte valid signal bwl_n is high, execute low-byte transmission.  

T5: When the high-byte valid signal bwh_n is high, execute high-byte transmission.  

T6: The CPU completes the read and write operation, and the relevant control signals are cleared.  

Among them, the DONE signal is used to indicate whether the read and write are completed. Only when DONE is high, it indicates that the read and write are completed, and the next read and write operation can be performed. The RDY signal indicates whether the SDRAM is ready to accept the CPU access. It is controlled by the SDRAM write request signal (IN_REQ = 1) and the read valid signal (OUT_VALID = 1). The pseudo code of its generation process is shown in Table 5.  


  
According to the structure of the single-chip computer system-level design, the 8086 IP soft core, 8255 IP soft core, SDRAM controller, SDRAM model IS42S16400, AHB bus IP soft core and decoder IP soft core that have been written are called.  

Connect the corresponding input and output ports, assign values ​​to the 8086 related input ports, and leave the unused output ports hanging to complete the RTL level design of the single-chip computer system.  

4 Simulation and verification of single-chip computer system  

The RTL level design of the single-chip computer is only a part of the entire design process. In order to ensure the success of the final design, it must be fully simulated by software and verified by hardware, including building a test platform, designing test plans, analyzing simulation results, and realizing FPGA verification.  

4.1 Design of the test plan  

Based on the completion of the single-chip computer system including the 8255 application circuit, it is required to realize the function of eight switch quantities controlling the on and off of eight LED lights. Connect the eight switch quantities to PA0~PA7 of 8255; connect the eight LED light drive circuits to PC0~PC7 of 8255. Under the control of 8086 CPU, read the eight switch quantities connected to the PA port of 8255 through the bus, send the switch values ​​to SDRAM for storage, and then read the switch quantities from SDRAM and send them to the PC port of 8255 to drive the eight LED lights on or off.  

4.2 Analysis of simulation results  

The RTL level simulation waveform of the minimum set of single-chip computers is shown in Figure 7. Under the control of the 8086 CPU, the 8255 interface reads the eight switch quantities 11000010 connected to the 8255 PA port and sends them to the 8255 PC port to drive the output logic value 11000010.  


  
The design is successfully compiled using the Quartus II software, and the results generated by the layout and routing are downloaded to the FPGA to obtain the actual circuit equivalent to the design. The actual circuit is tested with the test system to verify the correctness of the design. The verification results of the FPGA are read and displayed by the logic analyzer, as shown in Figure 8.  


  
5 Conclusion  

Under the guidance of integrated circuit design methodology, this paper explores the architecture of a single-chip computer platform based on the 8086 CPU core, and studies its integration with peripheral IPs such as AMBA bus, SDRAM, and 8255. On this basis, a single-chip computer system based on the 8086 IP soft core is designed, and FPGA function demonstration is realized. In the subsequent work, we will consider further expanding the CPU peripheral interface IP soft core; integrating the DMA controller to realize the VGA display function; adding the DOS operating system to the 8086 single-chip computer platform, and developing device drivers and application software under the operating system.