Writing a simple makefile

    There are three main contents in the makefile:

    1. Variable declaration:

        Variable declaration is a basic strict character replacement operation.

        For example, in the previous statement: objects = program.o foo.o utils.o

        Then all subsequent $(objects) or ${objects} will be automatically replaced with the above character sequence, and it will be a strict replacement, that is, without spaces.

    2. Mapping rules

    3. Command:

    Mapping rules and commands are usually combined to form a structure like this:

    target... : prerequisites..

             command

    It can be simply understood as taking the corresponding commands described later (the commands here are shell commands in Linux) through prerequisites, that is, the prerequisite dependency files, and then (usually) generating the file target. A blank space is left in front of the command according to the following tab to indicate that it is a command.

    Some targets do not have prerequisites, which means that the following commands are executed unconditionally.

    The overall purpose of this structure is to tell make whether the target is out of date, which depends on its dependent files. If the target does not exist, it is also considered out of date. Then if it is out of date, update it by running the following command.

2. In the previous article, we created two makefiles in emacs, but they were empty and had no content. Now we fill them with the following content: (This is a simple example, but it is a good introduction.)

The contents of the makefile in the main directory of /project/hello are as follows:

    prefix = /usr/local

exec_prefix = $(prefix)

bindir = $(exec_prefix)/bin

export prefix

export exec_prefix

export bindir

all clean install uninstall :   

             cd src && $(MAKE) $@

.PHONY: all clean install uninstall

The contents of the makefile in the /project/hello/ src directory are as follows:

all: hello

hello: main.c

         $(CC) -o $@ main.c

clean:

         rm hello

install:

         install -d $(bindir)

         install -m 0755 hello $(bindir)

uninstall:

         rm $(bindir)/hello

.PHONY: all clean install uninstall

We will explain it in detail later, let's take a look at the operation first:

Now makefile supports these four commands: make, make install, make clean and make uninstall.

We can see from the figure above that we can call the program hello we generated directly from the terminal, and it will return "hello, the world!".

    First, let's look at the makefile in the main directory. The first part is the variable declaration, which will be discussed later. Then there is the export variable. This is the main makefile in the main directory that can use this command, which means sharing the variable with the makefile in the sub-directory. [page]

    Then we see

all clean install uninstall :

         cd  src  && $(MAKE) $@

.PHONY: all clean install uninstall

This is actually a jump structure. First, let's introduce what .PHONY means. As mentioned earlier, each target is a file to be generated by default, but the target following .PHONY: means that these targets do not need to generate files. So in general, all, clean, install, and uninstall here are some execution commands that do not have dependent files and do not need to generate the final target file. These execution commands are the make, make install, make clean, and make uninstall mentioned earlier. The meaning of make is actually make all, and there is no difference between these two commands.

    Then we see the command, cd src, which is easy to understand, it jumps to the src directory. Then the && symbol means logical AND, that is, the following command is executed after the previous command is executed. The following $(MAKE) may be a variable with a system default value, which should be make here. The $@ symbol means to refer to the current target . For example, if I make clean now, the command will eventually look like this:

    cd src &&make clean

    Then the next make clean command is actually for the makefile in the src subdirectory. We can see the simple:

clean:

    rm hello

That is, just delete the generated executable file hello.

Then let's look at how the makefile in the subdirectory handles the make all command:

all: hello

hello: main.c

    $(CC) -o $@ main.c

We can see that first it says that all depends on hello, and then hello depends on main.c. To generate or update hello, you need to execute the following command:

cc -o hello main.c

The $(CC) above is also a variable with the system default value, which is cc, but in GNU/LINUX systems, the gcc tool may be called. The option -o at the end means to compile and link and then generate a file with the name at the end. The name here is hello.

Then let's look at the execution of the make install command:

install:

install -d $(bindir)

install -m 0755 hello $(bindir)

As mentioned above, this variable is inherited from the definition in the makefile file of the main directory, and then translated into $(bindir) is /usr/local/bin. Linux system has two locations for storing commands that can be directly called from the terminal, and the other one is /usr/bin . The structure inside the /usr /local folder is very similar to the structure inside /usr. It seems that /usr is a space for software inside the system, but this rule is not rigid.

The uninstall command is an operation to delete the hello file in the corresponding location. So now we will talk about the install command in Linux.

    The first install command followed by the -d option means directory confirmation, which I think is a bit redundant here.

    The second install command with the -m option means to copy hello to the specified directory, and then set the permissions of the corresponding file, that is, the hello file, to 0755. I don't think there is anything to say about permissions here. The second install command can be used here. The process is to copy, add permissions, and update the timestamp.