SPI Interface Introduction

   I came across a flash using the SPI interface these days, and then I realized that flash can also be serial. It seems that I was really ignorant before. I found some information about the SPI interface, but it was not complete. Later, I found some English information, translated it, and combined it with my personal understanding to make an article. I hope it will be helpful to beginners.

   The full name of the SPI interface is "Serial Peripheral Interface", which means serial peripheral interface. It was first defined by Motorola on its MC68HCXX series processors. The SPI interface is mainly used in EEPROM, FLASH, real-time clock, AD converter, and between digital signal processors and digital signal decoders.

   The SPI interface is a synchronous serial data transmission between the CPU and peripheral low-speed devices. Under the shift pulse of the master device, the data is transmitted bit by bit, with the high bit first and the low bit last. It is full-duplex communication. The data transmission speed is generally faster than the I2C bus, and the speed can reach several Mbps.

   The SPI interface works in a master-slave mode. This mode usually has a master device and one or more slave devices. Its interface includes the following four signals:

(1) MOSI - master device data output, slave device data input
(2) MISO - master device data input, slave device data output
(3) SCLK - clock signal, generated by the master device
(4) /SS - slave device enable signal, controlled by the master device



      In point-to-point communication, the SPI interface does not require addressing operations and is full-duplex communication, which is simple and efficient.
      In a system with multiple slave devices, each slave device requires an independent enable signal, and the hardware is slightly more complicated than the I2C system.



    The SPI interface is actually two simple shift registers in the internal hardware. The data transmitted is 8 bits. Under the slave device enable signal and shift pulse generated by the master device, the data is transmitted bit by bit, with the high bit first and the low bit last. As shown in the figure below, the data changes on the falling edge of SCLK, and a bit of data is stored in the shift register at the same time.
   
     Diagram of the internal hardware of the SPI interface:
         
     Finally, a disadvantage of the SPI interface is that there is no specified flow control and no response mechanism to confirm whether the data has been received.