The clock selection and frequency division procedures of the msp430G2553 microcontroller are as follows:
#include "msp430G2553.h"
#define unchar unsigned char
#define uint unsigned int
uint Fre;
int main( void )
{
// Stop watchdog timer to prevent time out reset
WDTCTL = WDTPW + WDTHOLD;
BCSCTL2 |=SELM_1+DIVM_0;
P1DIR &=~BIT3;
P1REN | =BIT3;
P1OUT |=BIT3;
P1DIR |=BIT0;
P1IE |=BIT3;
P1IES &=~BIT3;
_EINT();
while(1)
{
P1OUT ^=BIT0;
__delay_cycles(1000000);
}
}
#pragma vector=PORT1_VECTOR
__interrupt void PORTP13(void)
{
uint temp,pushkey=0;
pushkey=BIT3 & (~P1DIR);
__delay_cycles(100000);
temp=P1IN;
if((~temp) & BIT3==pushkey)
{
Fre++;
if(Fre>3) Fre=0;
switch(Fre)
{
case 0: DCOCTL=CALDCO_1MHZ;BCSCTL1 = CALBC1_1MHZ;break;
case 1: DCOCTL=CALDCO_8MHZ;BCSCTL1 = CALBC1_8MHZ;break;
case 2: DCOCTL=CALDCO_12MHZ;BCSCTL1 = CALBC1_12MHZ;break;
case 3: DCOCTL=CALDCO_16MHZ;BCSCTL1 = CALBC1_16MHZ;break;
default:break;
}
}
P1IFG &=~BIT3;
}
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Professor at Beihang University, dedicated to promoting microcontrollers and embedded systems for over 20 years.
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