Design of intelligent video monitoring circuit for access control system

　　This article mainly introduces the design of multi-channel video acquisition circuit, USB interface circuit, serial port conversion and communication circuit in the hardware design of video monitoring host system based on FPGA. The parallel use of single-chip microcomputer and FPGA can make data transmission more coordinated and improve system reliability. The hardware system can realize the storage and transmission of video information, automatic storage of alarm information, USB information copy, allow multi-channel simultaneous alarm and remote control of PTZ, etc., which further improves the working efficiency of monitoring control system.

　　Design of Video Signal Selection Circuit

　　The system's external front-end equipment camera records the video of each access control location and transmits it to the video signal selection circuit of the host control system through the video transmission line. The selection circuit has four video inputs, four video outputs, and a public video output. On the one hand, the video signal is output from the four-way video after impedance matching by MAX4090, so that the management personnel can view the on-site activities of the access control. At the same time, the public video terminal can not only output one video, but also store the video information through the video processing board and transmit the video information through the network; the output video signal is converted into a visual signal through the control of FPGA and stored in the PC. At the same time, FPGA can continuously detect the amount of video alarm signal to trigger the alarm signal.

　　As shown in Figure 2, there is only one input, one output and one public video circuit diagram as a schematic diagram of the video selection circuit system. J1 is the video signal input terminal, J5 and J9 are the video signal output terminals. CON2 is a short-circuit jumper to connect and disconnect the corresponding channels. When CON2 is disconnected, the corresponding channel is connected, the video signal is input from the left, and is output from the right after matching; when CON2 is connected, the video signal cannot be matched after input and is directly output. Then MAX4090 is used for impedance matching to select and output multiple videos. This circuit uses AC coupling output. From the technical characteristics, the most common method to output video signals to media display devices is AC coupling, which allows the receiving circuit to establish a common mode level at its own input terminal, which is independent of the DC level of the input video signal. A 75-ohm series resistor should be placed as close to the output terminal as possible, which helps to isolate the downstream parasitic interference generated from the output terminal and provide the best signal conditions.

　　Design of USB interface circuit

　　In order to conveniently use the USB camera and USB data download channel, the system always needs to design a USB interface circuit.

　　The USB circuit is shown in Figure 3. The USB function uses the common CH375 chip as the USB interface control chip. CH375 is a universal interface chip for the USB bus, supporting USB-HOST host mode and USB-DEVICE/SLAVE device mode. On the local side, CH375 has an 8-bit data bus and read, write, chip select control lines and interrupt output, which can be easily connected to the system bus of controllers such as microcontrollers/DSP/MCU/MPU. In USB host mode, CH375 also provides a serial communication mode, which is connected to microcontrollers/DSP/MCU/MPU through serial input, serial output and interrupt output. CH375 has two connection modes with the microcontroller: serial port and parallel port. In this system, the CH375 chip is connected to the sub-control chip in parallel mode. The TXD pin of CH375 is grounded or directly grounded through a pull-down resistor of about 1 kilo-ohm, so that CH375 works in parallel mode. This parallel connection mode greatly improves the data transmission rate.

　　Design of EPROM and single chip computer storage circuit for FPGA

　　The system uses AT24C512EEPROM device as the main storage chip, its storage capacity is 512K and the microcontroller's read and write operations on AT24C51 series E2PROM fully comply with the rules of master-receive-slave-transmit and master-transmit-slave-receive of 12C bus. Data transmission consists of four parts: start (START) condition, slave address transmission, data transmission and stop (STOP) condition. One bit of data is transmitted during each clock high level, and the data on the SDA line must remain stable when the SCL line is high, otherwise it will be considered as a control signal. The advantages of this design are reflected in its simplicity and effectiveness.

　　As shown in the circuit in Figure 4, A0, A1, and WP are generally connected to VCC or GND, and SCL and SDA are connected to pull-up resistors (the resistance of the pull-up resistor can be selected by referring to the relevant data manual, usually 5K to 10K resistors can be selected, and the resistance selected in this design is 10K) and then connected to the ordinary I/O port of the microcontroller, so that the microcontroller can operate AT24C512. Before starting the operation of AT24C512, you need to send an 8-bit address word to select the chip for reading and writing. It should be noted that "10100" is the first 5 binary bits fixed by AT24C512; A0 and A1 are used to distinguish multiple AT24C512s; R/W is the read and write operation bit, 1 indicates a read operation, and 0 indicates a write operation. There are 512 pages inside the AT24C512, each page is 128 bytes, and the address of any unit is

　　16 bits, address range is 0000-0FFFFH. Although both FPGA chip and MCU have the function of reading and writing EEPROM, it does not mean that they have their own independent EEPROM chips, but two MCUs reuse EEPROM chips. If two chips read and write EEPROM chips at the same time, the MCU will definitely freeze, so a strict mechanism is needed to ensure that two MCUs will not read or write EPROM chips at the same time. This mechanism is called EPROM multiplexing relationship, that is, a handshake signal is used to coordinate the use of the two.

　　AC coupling technology is used in the video selection circuit, which is conducive to maintaining the transmission of high-definition video signals. At the same time, FPGA is used as the central control part, and two parallel single-chip microcomputers are used as auxiliary control chips, one for USB interface data control and transmission, and the other for other interface operations and external storage control. It not only coordinates the real-time monitoring and transmission of video signals, but also ensures that the FPGA processing is not affected by external circuits, greatly improving the work efficiency of the system.