NRZ-HDB3 code converter for high-speed long-distance communication

The commonly used NRZ code is not suitable for transmission in high-speed and long-distance data communication channels, so another code, HDB3 code, is selected. HDB3 code is an important coding method for serial data transmission. Compared with the most commonly used NRZ code, HDB3 has many advantages, such as eliminating the DC component of NRZ code and having better anti-interference performance for clock recovery, which makes it more suitable for long-distance channel transmission. E1 signals use HDB3 coding method with a rate of 2.048Mbps. It can be transmitted for 1.5km on RJ45 balanced twisted pair with characteristic impedance of 120Ω, which can meet the high-speed and long-distance transmission of data in most cases. When the data rate is less than the high-speed rate of 2.048Mbps, the data rate can be increased by inserting additional data bits.

The E1 transceiver chip DS2153Q fully complies with the E1 signal standard and has a peripheral microcontroller interface, which greatly improves the availability of the chip. E1 has three modes: framing, multi-framing and unframing. In the framed E1, the 0th time slot is used to transmit frame synchronization data, and the remaining 31 time slots can be used to transmit valid data; in the multi-frame E1, in addition to the 0th time slot, the 16th time slot is used to transmit signaling, and only the 1st to 15th, 17th to 31st, a total of 30 time slots can be used to transmit valid data; in the unframed E1, all 32 time slots can be used to transmit valid data. The E1 of the NRZHDB3 code converter proposed in this article works in unframed mode, that is, all 32 time slots of E1 are used to transmit valid data.

1 Brief Introduction of E1 Transceiver Chip DS2153Q DS2153Q is a T1/E1 transceiver chip of Dallas Company, which complies with the latest E1 line standards, including ITU G.703, G.704, G.706, G.823, I.431, ETSI300 011, 300 233, TBR12 and TBR13, etc. The chip can complete the conversion between NRZ and HDB3 codes, and the code rate can reach 2.048Mb/s. In addition, the chip integrates the recovery circuit when receiving NRZ code data, which is more conducive to the subsequent receiving circuit. The on-chip D/A can realize the output waveform of G.703 standard, which is suitable for twisted pair with 75Ω and 120Ω characteristic impedance, and has a complete data flow status monitoring function, which can indicate the transmission status of data flow in real time. The peripheral microcontroller interface of DS2153Q makes it easy to connect with MCU interface such as single-chip microcomputer. The 71 internal 8-bit registers allow users to configure the functions and monitor the status of the DS2135Q through the MCU. These registers mainly include receive control registers, transmit control registers, general control registers, interrupt mask registers, and working status registers. Figure 1 is the internal structure of the DS2135Q.

2. Design of Code Converter Circuit The NRZ-DB3 code converter is used for the conversion from NRZ code to HDB3 code and from HDB3 code to NRZ code. The design uses the dedicated E1 receiving chip DS2153Q and the single-chip microcomputer AT89C51 to realize the conversion function of the code system. The code converter converts the input NRZ to HDB3 code output, and converts the received data on the E1 line into HRZ code, and recovers the data clock for use by the subsequent data receiving unit. AT89C51 is an 8-bit single-chip microcomputer of Atmel Company, which is responsible for controlling the working mode and status monitoring of the communication chip DS2153Q, so that it can complete the conversion from NRZ code to HDB3 code and from HDB3 code to HRZ code. At the same time, the peripheral circuit of the single-chip microcomputer also includes the μP monitoring circuit IMP813L, which is used to improve the anti-interference ability and reliability of the code converter. Figure 2 is the structural block diagram of the code converter. The parallel data/address line of DS2153Q is connected to the P0 port of the microcontroller; the chip select signal uses P2.0 of the microcontroller; the read and write signals of the microcontroller are connected to the read and write signals of DS2153Q; at the same time, the two interrupt request lines of DS2153 are connected to INT0 and INT1 of the microcontroller. In this way, DS2153Q can timely notify the microcontroller of its own working status through interrupts. The circuit connection diagram of AT89C51 and DS2153Q is shown in Figure 3. Through the above hard connection, the microcontroller can control and monitor the status of DS2153Q. Figure 3 AT89C51 and DS2153Q circuit connection diagram The code converter uses IMP813L as the μP monitoring circuit to achieve reliable power-on reset and watchdog control. The clock signal of DS2153Q is realized by dividing the clock signal of the microcontroller by two. The microcontroller uses a 16.384MHz clock signal, and after using 74HC74 to divide it by two, a frequency signal of 8.192MHz is obtained as the input clock of DS2153Q. In the circuit design of DS2153Q, in order to make it work in unframed mode, all the data to be sent is input from the TSER pin, and the pins TLINK and TSER need to be short-circuited.

The photodiode is used as the working indicator of the converter, and it can visually judge whether the current data conversion is normal. The code converter uses the RJ45 balanced twisted pair with a characteristic impedance of 120Ω for data transmission. The DS2153Q transceiver circuit is shown in Figure 4, and the input-output turns ratio of the transmission transformer is 1:1.36.

3. MCU Control Program Design

The converter microcontroller control program consists of two parts: DS2153Q function configuration and DS2153Q working status monitoring. DS2153Q function configuration realizes the normal operation of HDB3 code; DS2153Q working status monitoring is used to obtain whether the current converter is working normally in real time, and report and indicate in time.

3.1 DS2153Q Function Configuration After the converter is powered on, the μP monitoring circuit will first perform an effective reset to ensure the normal initialization of the single-chip microcomputer, and the single-chip microcomputer will enter the configuration process of the communication chip DS2153Q. ① Initialize the test register, write 0 to the corresponding test register. ② Configure the receive control register (RCR), including the receive frame mode, automatic resynchronization enable, resynchronization criteria and receive dynamic storage function, so that the DS2153Q receiving chip works in Auto Resync and Disable Elastic Store. ③ Configure the transmit control register (TCR), including the transmit frame mode, automatic setting of fault bits and function selection of 16-bit pins, so that the DS2153Q transmitting unit works in E-bits not automatically set in the transmit direction, and set the function of the 16 pins according to the current conversion mode, 0=Receive Loss of Sync(RLOS), 1=Loss of Transmit Clock(LOTC). ④Configure the common control register (CCR), enable the reception and transmission of DS2153Q and HDB3 code, configure the error counter update time, prohibit dynamic storage of transmission data, etc. ⑤Initialize the interrupt mask register, enable the reception carrier loss, reception loss interrupt, reception data all 0 and all 1 interrupt, and enable the transmission clock loss interrupt. Through these interrupts, the microcontroller can timely know the working status of DS2153Q and realize the microcontroller's monitoring of it.

⑥ Initialize the transmission line interface unit, write 0 to the LIRST data bit, and then write 1 to make the transmission line interface enter the normal working mode. ⑦ Initialize the transmission line interface control register, including transmission waveform selection, receiving equalizer gain selection, anti-jitter suppressor selection, etc. The microcontroller control flow is shown in Figure 5. The following is the function configuration program (part) of DS2153Q. ;************************************************************; MOV A, 02H MOV DPTR, #RCR1 MOVX @DPTR, A ;Write register RCR1, enable automatic resynchronization NOP MOV A, #04H MOV DPTR, #RCR2 MOVX @DPTR, A ;Write register RCR2, disable elastic storage function NOP MOV A, #41H MOV DPTR, #TCR1 MOVX @DPTR, A ;Write register TCR1, TSYNC is output mode NOP MOV A, #0F9H MOV DPTR, #TCR2 MOVX @DPTR, A ;Write register TCR2, E data bit disables automatic setting NOP MOV A, #44H MOV DPTR, #CCR1 MOVX @DPTR, A ;Write register CCR1, allow receiving and sending NOP ;HDB3 code NOV A, #00H MOV DPTR, #CCR2 MOVX @DPTR, A ; Write register CCR2, configure error count register NOP ;************************************************************

3.2 DS2153Q status monitoring design

After completing the register configuration of DS2153Q, the microcontroller enters the transmission status monitoring program to monitor the normal operation of DS2153Q in real time, including reading the status register and responding to DS2153Q interrupts, and judges faults and reports them in time. (1) Transmission status monitoring

The transmission status monitoring of DS2153Q is realized through INT1 of the microcontroller. When the transmission status position of the status register is 1, DS2153Q generates an interrupt, and the microcontroller responds to the interrupt to read the fault bit of the current status register. After reading, it is necessary to write 1 to the specific status bit of the status register to ensure that the fault can be set correctly in the future. The status monitoring program (interrupt 1 handler) for NRZ transmission clock loss fault is given below. MOV DPTR, #SR2; Read DS2153Q status register 2 NOP MOVX A, @DPTR ANL A, #04H JNZ ERROR SJMP FAVER ERROR: SETB ERR_SR SJMP LOCKE FAVER: CLR ERR_SR LOCKE: JNB ERR_SR, WORK; Determine whether the data transmission clock is lost or not SETB P1.0; Fault, the working indicator diode is off SJMP EVER WORK: CLR P1.0; Normal, the working indicator diode is on EVER: MOV DPTR, #SR2 MOV A, #04H MOVX @DPTR, A RETI (2) Receiving status monitoring The receiving status monitoring of DS2153Q is realized through INT0 of the microcontroller. When the sending status position of the status register is 1, DS2153Q generates an interrupt, and the microcontroller responds to the interrupt to read the fault bit of the current status register. After reading, it is necessary to write 1 to the specific status bit of the status register to ensure that the subsequent faults can be correctly set. The following is a status monitoring program (interrupt 0 handler) for the HDB3 code receiving carrier loss fault. MOV DPTR, #SR1; Read DS2153Q status register 21 NOP MOVX A, @DPTR ANL A, #02H JNZ ERROR SJMP FAVER EPPOR: SETB ERR_SR SJMP LOCKE FAVER: CLR ERR_SR LOCKE: JNB ERR_SR, WORK; Determine whether the receiving carrier is lost or not SETB P1.0; Fault, work indicator diode is off SJMP EVER WORK: CLR P1.0; Normal, work indicator diode is on EVER: MOV DPTR, #SR1 MOV A, #02H MOVX @DPTR, A RETI 4 In summary, the NRZ-DB3 code converter uses the E1 transceiver chip DS2153Q to complete the conversion from NRZ code to HDB3 code and from HDB3 code to NRZ code, realizing high-speed and long-distance data transmission, and enabling the 2.048Mb/s data stream to achieve a transmission distance of 1.5km on the twisted pair cable of the RJ45 interface, meeting most high-speed data transmission situations.