The evolution of single-chip microcomputer application to single-chip system design

　　1. Background of Changes in Embedded System Design Methods

　　The evolution of embedded system design methods is generally driven by application requirements and IT technology.

　　1 With the continuous innovation and development of microelectronics technology, the integration and process level of large-scale integrated circuits are constantly improving. The combination of silicon materials and human wisdom has produced a large number of low-cost, high-reliability and high-precision microelectronic structural modules, promoting the development of a new technical field and industry. The device programmable ideas and microprocessor (device) technology developed on this basis can use software to change and realize the functions of hardware. The large-scale application of microprocessors and various programmable large-scale integrated special circuits and semi-custom devices has created a brand new application world, which has widely affected and gradually changed human production, life, learning and other social activities.

　　2. The substantial improvement in the performance of computer hardware platforms has enabled the implementation of many complex algorithms and user-friendly interfaces, greatly improved work efficiency, and provided a physical basis for the auxiliary design of complex embedded systems.

　　3. High-performance EDA comprehensive development tools (platforms) have made great progress, and their automation and intelligence levels have been continuously improved, providing complex embedded system designs with an integrated development environment that is easy to learn and easy to use, integrating editing, layout, routing, compilation, synthesis, simulation, testing, verification, and device programming for different purposes and levels.

　　4. The development of hardware description language HDL (Hardware Description Language) provides a working medium for building various hardware models for complex electronic system design. It has strong description and abstraction capabilities, and has brought major changes to hardware circuits, especially semi-custom large-scale integrated circuit design. At present, the most commonly used ones are VHDL, which has become the IEEE STD1076 standard, Verilog HDL, which has become the IEEE STD 1364 standard, and AHDL, which is the corporate standard of Altera Corporation.

　　Due to the development and standardization of HDL, a number of companies have emerged in the world that use HDL to professionally design various integrated circuit functional modules. Their mission is to use HDL to describe the functions and structures of integrated circuits according to common or special functions, and to form IP core modules of different levels through different levels of verification for chip designers to assemble or integrate.

　　An IP (Intellectual Property) core module is a pre-designed and even verified integrated circuit, device or component with a certain function. It has several different forms. IP core modules have three different levels of design: behavior, structure and physical, corresponding to the "soft IP core" that mainly describes the functional behavior, the "firm IP core" that completes the structural description, and the "hard IP core" that is based on the physical description and has been process-verified. This is equivalent to the design technology of the blank, semi-finished and finished products of integrated circuits (devices or components).

　　Soft IP cores are usually submitted to users in some HDL text. They have been optimized and functionally verified at the behavioral level, but do not contain any specific physical information. Based on this, users can synthesize the correct gate circuit level netlist and carry out subsequent structural design. They have the greatest flexibility and can be easily integrated with other external logic circuits with the help of EDA synthesis tools. According to various semiconductor processes, they can be designed into devices with different performances. The total number of gates in the circuit structure of commercialized soft IP cores is generally more than 5,000. However, if the subsequent design is improper, the entire result may fail. Soft IP cores are also called virtual devices.

　　The hard IP core is a physical design based on a certain semiconductor process. It has a fixed topology layout and specific process, and has been verified by the process with guaranteed performance. It is provided to users in the form of circuit physical structure mask layout and a full set of process files, which is a full set of technology that can be used right away.

　　The design depth of the solid IP core is between that of the soft IP core and the hard IP core. In addition to completing all the designs of the hard IP core, it also completes the design links such as gate-level synthesis and timing simulation. It is usually submitted to users in the form of a gate-level netlist.

　　Manufacturers such as TI, Philips and Atmel have obtained Intel's authorization to use the MCS-51 IP core module and combine their own expertise to develop unique microcontrollers that are compatible with Intel MCS-51.

　　Commonly used IP core modules include various CPUs (32/64-bit CISC/RISC CPUs or 8/16-bit microcontrollers/single-chip microcomputers, such as 8051, etc.), 32/64-bit DSPs (such as 320C30), DRAM, SRAM, EEPROM, Flash memory, A/D, D/A, MPEG/JPEG, USB, PCI, standard interfaces, network units, compilers, encoders/decoders, and analog device modules, etc. The rich IP core module library provides a basic guarantee for the rapid design of application-specific integrated circuits and single-chip systems and for occupying the market as soon as possible.

　　5. The progress of software technology, especially the introduction of embedded real-time operating system EOS (Embedded Operation System), provides underlying support and efficient development platform for the development of complex embedded system application software. EOS is a powerful and widely used real-time multi-task system software. It generally has various system resource management functions of operating systems. Users can implement various resource management through API function calls. User programs can be developed and run on the basis of EOS. Compared with the OS in general system machines, it has the characteristics of short and powerful system kernel, low overhead, strong real-time performance and high reliability. The perfect EOS also provides drivers for various devices. In order to adapt to network applications and Internet applications, it can also provide TCP/IP protocol support. Currently popular EOS include 3Com's Palm OS, Microsoft's Windows CE and Windows NT Embedded4.0, Japan's Tokyo University's Tron and various open source embedded Linux, as well as the domestically developed Hopen OS of Kaisi Group and Zhejiang University's HBOS.

　　2. Changes in Embedded System Design Methods

　　In the past, programmers who were good at software design generally kept their distance from hardware circuit design, and hardware design and software design were considered to be technologies of completely different natures.

　　With the development of electronic information technology, designers with a background in electronic engineering often gradually get involved in software programming. The main form is to learn the corresponding assembly language programming through the application of microcontrollers (commonly known as single-chip microcomputers in China). When designing a larger-scale distributed control system, it is inevitable to use the popular PC as the upper machine, so as to further learn to use Quick BASIC, C, C++, VC and VB and other high-level languages ​​to program the system program, design the system interface, and form a centralized distributed control system through multi-machine communication with the front-end machine controlled by the single-chip microcomputer.

　　Designers who come from software programming backgrounds are rarely interested in learning application circuit design. However, with the rapid development of computer technology, especially the invention of hardware description language HDL, the system hardware design method has changed. The hardware composition and behavior of digital systems can be completely described and simulated using HDL. In this case, designing hardware circuits is no longer the patent of hardware design engineers. Designers who are good at software programming can use HDL tools to describe the behavior, function, structure, data flow, signal connection relationship and timing relationship of hardware circuits, and design hardware systems that meet various requirements. [page]

　　EDA tools allow for two types of design input tools, which are adapted to the needs of hardware circuit designers and software programmers with different backgrounds. Designers with hardware backgrounds are allowed to use the schematic input method they are used to, while designers with software backgrounds are allowed to use the hardware description language input method. Since HDL description is used for input, it is closer to the system behavior description, and is easier to synthesize, transfer in the time domain, and modify. It can also establish design files independent of the process. Therefore, once people who are good at software programming have mastered HDL and some necessary hardware knowledge, they can often design better hardware circuits and systems than engineers accustomed to traditional design. Therefore, engineers accustomed to traditional design should learn to use HDL to describe and program.

　　3. Three levels of embedded system design

　　There are three different levels of embedded system design.

　　1 Level 1: Design method using PCB CAD software and ICE as main tools.

　　This is the method that has been used by microcontroller application system designers in my country in the past and up to now. The steps are abstract first and then concrete.

　　Abstract design mainly refines the system functions according to the functional requirements of the embedded application system, divides them into several functional modules, draws the system function block diagram, and then allocates hardware and software functions to the functional modules.

　　The specific design includes hardware design and software design. Hardware design mainly selects and combines the components needed for each functional module according to the performance parameter requirements. The basic principle of selection is to use the most cost-effective general components available on the market. If necessary, each part that is not sure should be tested, functionally inspected and performance tested separately, and a relatively optimized solution from module to system should be found, and a circuit schematic should be drawn. A key step in hardware design is to use printed circuit board (PCB) computer-aided design (CAD) software to layout and wire the components of the system, followed by printed circuit board processing, assembly and hardware debugging.

　　The largest workload is software design. Software design runs through the entire system design process, mainly including task analysis, resource allocation, module division, process design and refinement, coding debugging, etc. The workload of software design is mainly concentrated in program debugging, so software debugging tools are the key. The most commonly used and effective tool is the in-circuit emulator (ICE).

　　2 Level 2: Design method using EDA tool software and EOS as development platform.

　　With the development of microelectronics process technology, various general-purpose programmable semi-custom logic devices have emerged. In hardware design, designers can use these semi-custom devices to gradually turn several standard logic devices that were originally interconnected through printed circuit boards into application-specific integrated circuits (ASICs). In this way, the complexity of printed circuit board layout and wiring is converted into the complexity of configuration within semi-custom devices. However, the design of semi-custom devices does not require designers to have knowledge and experience in semiconductor processes and on-chip integrated circuit layout and wiring. As the scale of semi-custom devices becomes larger and larger, and more and more devices can be integrated, the cost of wiring, assembly and debugging of interconnected devices on printed circuit boards is reduced. This not only greatly reduces the area of ​​printed circuit boards and the number of connectors, reduces the overall cost of the system, and increases the flexibility of programmable applications, but more importantly, it reduces system power consumption, increases system operating speed, and greatly improves system reliability and safety.

　　In this way, hardware designers have gradually shifted from selecting and using standard general-purpose integrated circuit devices to designing and manufacturing some special-purpose integrated circuit devices by themselves, and these technologies are supported by various EDA tool software.

　　Semi-custom logic devices have gone through the development process of programmable logic arrays PLA, programmable array logic PAL, general array logic GAL, complex programmable logic devices CPLD and field programmable gate arrays FPGA. The trend is that the integration and speed are constantly improving, the functions are constantly enhanced, the structure tends to be more reasonable, and the use becomes more flexible and convenient.

　　Designers can use various EDA tools and standard CPLD and FPGA to design and manufacture large-scale integrated circuits for users. Then, through the bottom-up design method, the integrated circuits designed and manufactured with semi-custom devices, programmable peripheral devices, selected ASICs and embedded microprocessors or microcontrollers are laid out and wired on the printed circuit board to form a system.

　　3 Level 3: A design method that uses the IP core library as the design basis and uses software-hardware co-design technology.

　　After the 1990s, the design of integrated circuits was further transformed to integrated system design. At present, the system has entered the SOC (System on a chip) design stage and has begun to enter the practical stage. This design method is not to simply integrate all the integrated circuits needed by the system into one chip. If the system is implemented in this way, it is impossible to achieve the high density, high speed, high performance, small size, low voltage, low power consumption and other indicators required by the system, especially the low power consumption requirement. The design of the system should start from the performance requirements of the entire system, and closely combine the design of the microprocessor, model algorithm, chip structure, peripheral device circuits at all levels and even the device, and complete the function of the entire system on a single chip through the collaborative design of system software and hardware based on a new concept. Sometimes the system may also be built on several chips. Because, in fact, not all systems can be implemented on one chip; it may also lose its commercial value because the process cost of implementing a certain system on a chip is too high. At present, the practical single-chip system is still a simple single-chip system, such as smart IC cards. But several well-known semiconductor manufacturers are working intensively to research and develop complex single-chip systems such as single-chip PCs.

　　It is neither realistic nor necessary to design a monolithic system from scratch, because the design is immature and has not stood the test of time, and the system performance and quality cannot be guaranteed. In addition, the commercial value will be lost due to the long design cycle.

　　In order to speed up the design cycle of single-chip systems and improve the reliability of systems, the most effective way at present is to use mature and optimized IP core modules for design integration and secondary development through authorization, and use glue logic technology GLT (Glue Logic Technology) to embed these IP core modules into SOC. IP core modules are the basis of single-chip system design. Which level of IP core modules to purchase should be determined based on the existing foundation, time, funds and other conditions. Purchasing hard IP core modules has the lowest risk, but the highest cost, which is inevitable. But in general, by purchasing IP core modules, not only can development risks be reduced, but development costs can also be saved, because the cost of purchasing IP core modules is generally lower than the cost of designing and verifying them separately. Of course, not all the required IP core modules can be bought from the market. In order to monopolize the market, some companies are unwilling to license and transfer the key IP core modules they have developed (at least temporarily). Such IP core modules have to be developed by themselves.

　　Each of these three levels has its own scope of application. From the perspective of application development, the first two methods have been used for a long time. The third-level design method can only be used to design simple single-chip systems for general specific application personnel. Complex single-chip systems can only be designed and implemented by some large semiconductor manufacturers, and the single-chip systems implemented in this way are only those widely used and large-scale application systems that are worth investing in. There are also some application systems that are not suitable for single-chip implementation due to technical problems or commercial value issues. When they launch the corresponding single-chip system in the form of commodities, application personnel only need to choose it. Therefore, the three levels of design methods will coexist, and the latter will not simply replace the former. Junior application designers will mainly use the first method; experienced designers will mainly use the second method; very professional designers will use the third method to design and apply simple single-chip systems. But all designers can use the dedicated single-chip systems designed with the third method launched by major semiconductor manufacturers.

　　Conclusion

　　At present, the three levels of design in my country are in the form of "surface", "line" and "point". Electronic information system designers who are accustomed to the first level design method need to gradually transition and develop to the second level; the second level design method should gradually develop from "line" to "surface"; the third level design method requires relevant national departments to organize various forces to tackle key problems and coordinate development according to IT development strategies and plans. The third level design method should gradually develop from "point" to "line".