Design and implementation of a sine signal generator

　　0 Introduction

　　Sine signal source plays a very important role in laboratory and electronic engineering design, but the traditional sine signal source is generally expensive according to actual needs, has poor performance at low frequency output and is not easy to adjust automatically, and has poor engineering practicality. The design of this paper makes a sine signal generator at a low cost, which can be used as a general sine signal to stimulate the magnetic field measuring instrument in nuclear magnetic resonance, and can also be used as a teaching demonstration signal source for modulation.

　　The sine signal generator is mainly composed of two parts: the sine wave signal generator and the signal for generating amplitude modulation, frequency modulation, and keying. The sine wave signal generator adopts direct digital frequency synthesis DDS technology, realizes the sine signal lookup table and address scanning on the CPLD, and obtains the sine signal through D/A output. It has high frequency stability, wide frequency range, and easy to achieve frequency stepping of 100 Hz. The fully digital structure is easy to integrate, the output phase is continuous, and the frequency, phase, and amplitude can be program-controlled.

　　The generation of AM, FM and keying signals can be realized by using dedicated FM and AM chips, but the FM and AM functions realized by this method are better for a certain frequency and a certain modulation index and frequency deviation, and are difficult to realize when the carrier frequency is variable and the modulation index and frequency deviation are required to be set arbitrarily. This paper uses CPLD and AT89S52 microcontroller to not only realize a sine wave signal with adjustable frequency range, but also conveniently realizes FM, AM and keying PSK, ASK digital modulation functions by adding corresponding digital control algorithms inside CPLD, which is beneficial to improving the overall performance and working reliability of the system. The sine signal generation part can be realized in a CPLD (EP1K30), which greatly simplifies the hardware circuit, facilitates function expansion, and creates conditions for further system integration.

　　1 Theoretical analysis and calculation

　　1.1 Generation of Sine Waveform

　　The unidirectional DDS consists of a numerically controlled oscillator (NCO) consisting of an N-bit phase accumulator and a ROM read-only memory (sine lookup table), a digital-to-analog converter (DAC), and a low-pass smoothing filter (LPF). Figure 1 shows the basic structure of DDS.

　　In Figure 1, fc is the clock frequency, K is the frequency control word, N is the word length of the phase accumulator, M is the number of bits of the ROM address line, L is the width of the ROM data line, and fo is the output frequency. The phase accumulator is composed of a cascade of a full adder and an accumulator register. Under the control of the clock frequency fc, the input frequency control word K is accumulated, and an overflow occurs when the accumulation is full. The output of the phase accumulator corresponds to the phase of the synthetic periodic signal at that moment, and this phase is periodic and varies in the range of 0 to 2π. The number of bits of the phase accumulator is N, and the maximum output is 2N-1, corresponding to the phase of 2π. One accumulation outputs a corresponding phase code. The address is obtained by table lookup to obtain the signal amplitude value of the corresponding phase. After digital-to-analog conversion, a signal output waveform of a certain frequency can be obtained. The low-pass filter smoothes the output signal waveform to filter out noise and harmonics. Since the control word K is accumulated 2N/K times, the phase accumulator overflows and completes one cycle of operation, so the output frequency fo is determined by fc and K, that is, fo=fcK/2N and K<2N-1, and the minimum resolution of DDS can reach fc/2N. Theoretically, by setting the number of bits N of the DDS phase accumulator, the frequency control word K and the value of the clock frequency fc, an output of any frequency can be generated. According to the requirement of a frequency step of 100Hz, the number of bits of the accumulator is selected as 19 bits, and the clock frequency fc is calculated to be 52.4288 MHz. The cumulative error of the step is corrected by the software compensation method, and the existing 52.416 0 MHz crystal oscillator is used to fully and accurately achieve the requirement of a step of 100 Hz.

　　Figure 1 Schematic diagram of a DDS-based sinusoidal signal generator

　　1.2 Generate analog amplitude modulation signal

　　The process of using a modulation signal to control the amplitude of a high-frequency oscillation so that the amplitude changes in proportion to the modulation signal is called amplitude modulation. If the carrier is uc=Uc cosωct and the modulation signal is f(t)=cosΩt, then the amplitude modulated wave is

　　Ordinary amplitude modulation waves are realized by analog multipliers, but the peripheral circuits are complex, and changing the modulation index requires changing the parameters of the circuit components, which is cumbersome to implement. CPLD chips can be used in combination with DDS technology to flexibly realize digital amplitude modulation, as shown in Figure 2.

　　Figure 2 Amplitude modulation principle diagram

　　The waveform signal generated by DDS is used as a carrier wave, and a sine waveform storage table with a modulation signal of 1 kHz is made inside the single-chip microcomputer. The result of multiplying the modulation index ma (10%~100%) set by the keyboard with the data in the storage table is sent to the CPLD to multiply the waveform obtained by DDS, and then added with the DDS signal to generate the corresponding digital amplitude modulation wave code, and the analog amplitude modulation signal is obtained through D/A conversion.

　　1.3 Generate analog frequency modulation signal

　　In continuous wave modulation, the carrier can be expressed as uc=Uc cosωct, and the modulation signal is UΩ(t). The change in the instantaneous frequency of the FM wave is proportional to the modulation signal. Therefore, in addition to the carrier angular frequency ωc, the instantaneous angular frequency of the FM wave also has an additional part that is proportional to the modulation signal. In the formula, kf is the proportional coefficient, which is the frequency change caused by the unit modulation signal strength. The maximum value of △ωf(t) △ωf is called the maximum frequency deviation, which is reflected in the frequency as f(t)=fc+△fcos(2πft). The expression of the FM wave is:

　　Figure 3 is a CPLD digital frequency modulation circuit. When the frequency deviation is 5 K, the control word is 50. The cosine waveform is multiplied by 50 and added to the frequency control word transmitted by the microcontroller. It is sent to the DDS module and converted by D/A to output the frequency modulation wave. The design schematic is shown in Figure 4.

　　Figure 3 CPLD digital frequency modulation circuit diagram

　　Figure 4 Frequency modulation design principle diagram

　　1.4 Generate binary PSK and ASK signals

　　Using digital baseband signals to control the amplitude of high-frequency sine waves is called amplitude-shift keying (ASK). Inside the CPLD, it is only necessary to process the generated DDS waveform according to the set binary baseband sequence code. When the binary baseband sequence is 1, the waveform passes, and when the sequence is 0, the output is 0. The simulation waveform is shown in Figure 5. [page]

　　Figure 5 Binary ASK simulation waveform

　　Phase shift keying (PSK) is a digital baseband signal that controls the phase of the carrier. It uses different phases or phase changes of the carrier to transmit information. The implementation method of PSK is to switch the carrier phase between two different values ​​according to the two levels (or symbols) of the digital baseband signal. The two carrier phases usually differ by 180°. The waveform is shown in Figure 6.

　　Figure 6 Binary PSK simulation waveform

　　1.5 Output signal conditioning section

　　The D/A conversion circuit is shown in Figure 7. The 12-bit high-speed D/A device AD9713 is selected, which has better static performance and dynamic characteristics. The update rate of AD9713B can reach 100MS/s. Since this D/A converter is designed for applications such as DDS, waveform reconstruction and high-quality image signal processing, this chip is particularly outstanding in dynamic characteristics and has excellent harmonic suppression capabilities. The full-scale current output of AD9713 is determined by VCONTROLAMP IN and RSET. In Figure 7, AD9713 uses an internal reference voltage and the full-scale current output is -20 mA.

　　Figure 7 D/A conversion circuit

　　The amplitude adjustment circuit is composed of an amplifier. High-frequency signal amplification requires the amplifier to have sufficient output voltage conversion rate. In the case of a sine wave, the maximum slew rate required by the amplifier is SR=2πω=2πAf, where ω is the angular frequency of the signal, A is the signal amplitude, and f is the frequency. In addition, the amplitude adjustment circuit requires a low-resistance load, and the current output capability of the amplifier is also an important parameter. To output a 6 V signal on a 50 Ω load, the amplifier must have at least 120 mA of continuous current output capability. Considering the above reasons, this article selects AD's high-speed operational amplifier AD811 as the output amplifier. It is a broadband, high-speed current feedback operational amplifier, and its various parameters are very suitable for the above indicators: small signal bandwidth (when G=+2) reaches 120 MHz, voltage slew rate SR is 2 500 V/μs, total harmonic distortion THD is -74 dB (10 MHz), output current reaches 100 mA, and its short-circuit output current can reach 150mA.

　　The amplitude adjustment circuit is shown in Figure 8. In the figure, R3 and R4 act as shunts to limit the current used for I/V conversion. It is a high-speed amplifier circuit with current feedback. It converts the current output by AD9713 into voltage. The current through the feedback resistor Rf determines the amplitude of the AD811 output to be 6 V. In order to increase the load capacity of the post-stage, the post-stage voltage follower is designed. The last part of the analog output is the filter circuit. The selection of the filter mainly depends on the waveform to be output by the system. The peak-to-peak voltage on the 50 Ω load resistor is 6±1 V.

　　Figure 8 Amplitude adjustment circuit

　　1.6 Receiving and displaying frequency values

　　The keyboard and display part are used to realize the interaction between the user and the single chip microcomputer. The system uses the interrupt query method to receive the frequency value input through the keyboard. On the one hand, the frequency value is sent to the digital display interface for display, and on the other hand, it is converted into a frequency control word and sent to the phase accumulation module.

　　2 System Software Design

　　The MCU program is written in C language, compiled in Keil uV2 environment, and debugged with WAVE6000L simulator. The CPLD is developed under MAXPLUSⅡ and programmed in VHDL language.

　　As for the CPLD part, the phase measurement instrument and digital phase shift signal generator use the EP1K30TC144-3FPGA chip of ALTERA, and the schematic diagram has been analyzed in the previous part. As for the microcontroller part, the program flow chart is shown in Figure 9.

　　Figure 9 Program flow chart

　　3 Function and index test

　　The performance of the designed signal generator is tested using test instruments: EE1641B1 function signal generator/counter, DC regulated power supply GPS-3303C, 60 MHz oscilloscope TDS1002, high-frequency tester, etc. The frequency range, step, output voltage amplitude on a 50 Ω load, and distortion measurement of the sine wave are shown in Table 1, the frequency stability measurement is shown in Table 2, the amplitude modulation test with a step of 10% is shown in Table 3, the frequency modulation test with a modulation signal of 1 kHz is shown in Figure 10, and the binary PSK and ASK are shown in Figures 11 and 12. [page]

　　Table 1 Observation results of sine wave experiment

　　Table 2 Sine wave frequency stability test results

　　Table 3 Sine wave amplitude modulation test results

　　Figure 10 Sine wave frequency modulation test results

　　Figure 11 ASK signal test diagram

　　Figure 12 PSK signal test diagram

　　After testing, it can be obtained that the system designed in this paper can achieve the following performance indicators:

　　1) Sine wave output frequency range is 1 kHz～10 MHz.

　　2) With frequency setting function, the frequency step is 100 Hz.

　　3) The output signal frequency stability is better than 10-4.

　　4) The peak-to-peak value of the output voltage on a 50 Ω load resistor is Vopp ≥ 1 V.

　　5) There is no obvious distortion when observing the distortion with an oscilloscope.

　　A comprehensive analysis of the test results of various indicators shows that the design has a large frequency variation range, high signal stability, and good distortion, meeting the design requirements for good performance.

　　4 Conclusion

　　Based on CPLD and AT89S52 microcontroller, the sine signal generator implemented with DDS technology can achieve adjustable frequency, low distortion, small frequency step, high accuracy and other characteristics while ensuring the stable output of sine wave frequency. The generated sine signal source can be widely used in teaching or general industry and experimental occasions. The test results show that the design of the sine signal generator proposed in this paper is effective, easy to implement in engineering and has certain practicality.