Research and implementation of testing methods for Cortex-M3 microprocessor based on ARM technology

0 Introduction

With the development of semiconductor technology, the integrated circuit manufacturing process has developed from deep submicron to nanometer level. The significant improvement of transistor integration has increased the complexity of chips and the functions of single chips have become stronger and stronger. ARM was founded in Cambridge, UK in the 1990s, mainly selling licenses for chip design technology. Microprocessors using ARM technology intellectual property (IP core), namely ARM microprocessors, have been widely used in various product markets such as industrial control, consumer electronics, communication systems, network systems, and wireless systems. Microprocessor applications based on ARM technology account for more than 70% of the market share of 32-bit RISC microprocessors. The widespread application and development of ARM chips have also brought challenges to testing. Integrated circuit testing generally uses functional testing at actual speed, but the development of semiconductor technology has caused the test development engineering resources to grow geometrically. The performance of automatic test equipment (ATE) cannot keep up with the development of the increasing device I/O speed. At the same time, it is increasingly difficult to meet the high-resolution requirements of timing signals used in the testing of ARM and other microprocessors. Therefore, the performance of automatic test equipment must be continuously improved, resulting in rising testing costs. In addition, as the complexity of ARM chips increases, the workload of manually writing test vectors for functional testing is extremely huge. In fact, the workload of manually writing test vectors for an ARM chip may reach dozens of man-years or even more. Based on the working principle of the ARM Cortex core, this paper proposes an efficient test vector generation method and implements the test of the ARM Cortex-M3 core microprocessor on the BC3192 test system.

1 Microprocessor test method

Integrated circuit testing mainly includes functional testing and DC parameter testing, and microprocessor testing also includes functional and DC parameter testing. Microprocessors contain a rich instruction set, and there are many types of microprocessors. It is difficult to have a unified test specification between different microprocessors. In order to make the test universal, it is necessary to establish a unified model for microprocessor testing, as shown in Figure 1. The chip test system provides power and clock for the microprocessor under test, and can simulate the simulation communication interface of the microprocessor to control the operation of the microprocessor, and apply the excitation vector in conjunction with the simulation timing to achieve the test purpose.

According to the microprocessor simulation communication interface, there are two categories: one is the microprocessor with a simulation interface (such as JTAG), and the other is the microprocessor . For microprocessors equipped with a JTAG-like interface, the tester simulates a JTAG interface to perform functional or parameter tests on the chip under test. For chips that are not equipped with a simulation debugging interface, the test model can be selected according to the chip's external interface and boot mode.

1.1 Trace debug mode

Most microprocessors provide trace debugging interfaces, such as the most commonly used JTAG interface. In addition to supporting JTAG debugging, the Cortex-M3 core also provides a dedicated instruction trace unit (ITM). JTAG (Joint Test Action Group) is an international standard test protocol (IEEE 1149.1 compatible), mainly used for chip internal testing . Most advanced devices now support the JTAG protocol, such as ARM, DSP, FPGA devices, etc. The standard JTAG interface is 4-wire:

TMS, TCK, TDI, TDO are mode selection, clock, data input and data output lines respectively. JTAG was originally used to test chips, so using the JTAG interface to test microprocessors has many advantages.

Using the JTAG interface to simulate the microprocessor is to use the test system to simulate a JTAG interface with test vectors to achieve simulation control of the microprocessor. The core is the simulation of the state machine. Figure 2 shows the state transition diagram of the JTAG TAP controller used by the test system. JTAG communication control can be achieved by simulating state transitions through the tester.

JTAG has unified specifications at the physical layer and data link layer, but the simulation test protocols for different chips may be slightly different. In order to make the test model universal, we made an abstract layer for the JTAG interface of the test model, as shown in Figure 3. The abstract layer in the figure converts various types of control functions into data streams that the chip can recognize to control the working state of the chip under test. [page]

1.2 Boot Mode/FLASH Programming Mode

For microprocessors that are not equipped with simulation debugging interfaces, the boot function can be used to test the microprocessor. Because there is no simulation debugging function, simulation testing cannot be achieved. Therefore, in the test of this type of microprocessor, it is necessary to load the test code into the chip. Most microprocessor chips have a power-on boot function, which can be used to load the test code into the microprocessor to achieve functional and DC parameter testing. For microprocessors equipped with internal FLASH, the test code can be downloaded to the on-chip FLASH first to achieve functional and parameter testing of the microprocessor.

In order to achieve test control of the microprocessor, usually, the test system uses the on-chip communication interface of the microprocessor to communicate with the on-chip test program, and cooperate with each other to complete functional and parameter tests.

2 ARM Cortex-M3 Test

2.1 Introduction to the ARM Cortex-M3 Core

ARM Cortex-M series microprocessors are mainly used in low-cost and low-power applications, such as intelligent measurement, human-machine interface devices, automotive and industrial control systems, large household appliances, consumer products, and medical devices. Figure 4 is a simplified block diagram of the Cortex-M series microprocessor.

The ARM Cortex-M3 core is equipped with several debugging related features.

The most important thing is program execution control, including halting, single-stepping, instruction breakpoints, data observation points, register and memory access, performance profiling, and various tracing mechanisms. The debugging system of Cortex-M3 is based on ARM's latest CoreSight architecture. Although the core itself no longer contains a JTAG interface, it provides a bus interface for the debug access interface (DAP). Through DAP, you can access the chip's registers and system memory, and you can access it when the core is running, which provides interface support for chip testing. Microprocessors with integrated Cortex-M3 cores generally provide a debug port (DP) connected to the DAP. Currently available debug ports include SWJ-DP, which supports both traditional JTAG debugging and the new serial wire debugging protocol. The Cortex-M3 core can also mount an embedded trace macro unit (ETM). ETM can continuously send out trace information, which is sent to the outside of the kernel through the trace port interface unit (TPIU). For ARM chips with external integrated trace information analyzer, the executed instruction information output by TIPU can be captured and sent to the chip test system.

2.2 Test Vector Generation

Testing ARM chips with automatic test equipment (ATE) is a traditional testing technology. Its advantage is that test vectors can be flexibly compiled and focused on application-related functional modules and parameters. However, due to the considerable complexity of the functions and applications of ARM chips, the capabilities of the test system are also required to be high. This requires that the test equipment itself must have the ability to test various functional modules, including the ability to test logic, simulation, memory, high-speed or high-frequency circuits, etc. At the same time, it is best for each test channel of the test system to have its own independent testing capabilities, avoiding the use of resource sharing, so that it can be flexibly used in various test functions. Therefore, conventional ARM chip test equipment often requires a very high configuration to meet test needs.

The meaning of testing is very broad. As far as ARM chip testing is concerned, many types of tests can be defined, and different types of tests require different types of test vectors. Although the method of generating test vectors can be compiled manually, in most cases they need to be generated by a test vector generation tool (ATPG) to generate a relatively complete test set. The ARM chip testing method introduced in this article generates test code with the help of the corresponding ARM chip development tool, and then generates test vectors with a dedicated test vector generation tool. The advantage of this method is that it can generate test vectors for the test set that ARM chip application developers are concerned about, so it is relatively efficient and the test cost can be controlled at a relatively low level. In addition, a large number of ARM chip application software can be used for transcoding, which can greatly reduce the workload. The disadvantage is that it is not easy to use algorithms to automatically generate complete test code.

Figure 5 shows the ARM chip test vector generator. Test code can generally be obtained from the ARM chip development routine. The test vector is compiled into ARM chip executable code by the compiler, and then mixed with the stimulus vector and the expected vector to generate a complete AR chip test vector. The ARM chip test vector generation tool determines the test code through the time parameter. The timing relationship between the stimulus vector and the expected vector, the ARM chip time parameter can be obtained from the chip manual. After the test vector is generated, it is downloaded to the test system graphics card through the BC3192 integrated development environment, the test program is started, the stimulus vector is sequentially applied to the input port of the ARM chip under test, and the output end is monitored and compared to obtain the test results. In summary, the generation of test vectors is the core of ARM chip testing. The test vector generator described in this article generates test logic by inputting the ARM chip executable code and chip time parameters. It is easy to use. High efficiency, it has been used in the testing of multiple ARMCortex core microprocessors.

3 Conclusion

This paper analyzes the working principle and tracking debugging method of the ARM Cortex-M3 core, uses the general ARM integrated development environment, and combines the test vector generator of the BC3192V50 test system to quickly and efficiently generate microprocessor test vectors based on the ARM Cortex-M3 core, thereby completing functional and DC parameter testing. The method described in this case is also suitable for testing other microprocessors.