Data Acquisition System Based on S3C2410A and Multiple AD7656-1 Daisy Chain

Introduction
　　
In substation automation systems, it is often necessary to collect and process multiple three-phase voltage and current signals (such as real-time monitoring of power quality). At this time, it is necessary to achieve simultaneous and rapid data collection of multiple signals. The AD7656-1 of Analog Devices (ADD) is a 16-bit 6-channel analog/digital conversion chip. It contains 6 independent A/D converters inside and can perform A/D conversion at the same time. It has the advantages of high conversion accuracy, fast speed, low power consumption, large input analog signal amplitude, and high signal-to-noise ratio. Its outstanding feature is that it can realize data acquisition of multiple channels at the same time by cascading multiple AD7656-1 to form a daisy chain, and send data to the main control processor through one or more serial ports. With S3C2410A as the main control processor, multiple AD7656-1s form a daisy chain to realize multi-channel, high-precision ADC, which can greatly improve the signal acquisition and processing capabilities of the data acquisition system and has good application prospects.
　　
1 Features of AD7656-1
　　
Figure 1 is the internal functional block diagram of AD7656-1. Its main features are:
　　
6 independent 16-bit successive approximation (SAR) analog-to-digital converters.

The voltage range of the input signal (±10 V, ±5 V) can be set by pin or software.

The maximum throughput is 250 ksps.

Wide bandwidth input high signal-to-noise ratio: The signal-to-noise ratio (SNR) is 88 db when the input frequency is 10 kHz.

With on-chip 2.5 V reference voltage source and reference buffer.

Low power consumption, only 140 mW at 250 kSPS when powered by 5 V.

Supports parallel, serial and daisy chain interface modes.

High-speed serial interface, compatible with SPI/QSPI/MICROWIRE/DSP.

Adopts iCMOS manufacturing process, 64-pin LQFP package.

Application areas: transmission line monitoring system, instrumentation and control system, multi-axis positioning system.


　　
2 AD7656-1 daisy chain working principle and its configuration
　　
2.1 AD7656-1 Daisy Chain Working Principle
　　
AD7656-1 has two interface modes: serial interface mode and parallel interface mode. During data conversion, the three conversion signals CONVSTA/B/C are used to control the simultaneous sampling of each pair or every 4 or every 6 ADCs. If the three CONVST pins are connected together to receive the same sampling start signal, the six ADCs can be sampled simultaneously. At this time, multiple AD7656-1s can be cascaded to form a daisy chain, realizing simultaneous sampling of 6N (N=2, 3, ..., 8) ADC channels, as shown in Figure 2. At the rising edge of CONVSTX, the ADC is set to hold mode and the conversion begins. After the rising edge of CON-VSTX, the BUSY signal becomes high. The BUSY signal returns to a low level after 3μs, indicating that the conversion is in progress. At the falling edge of the BUSY signal, the ADC returns to the tracking mode. Data can be read from the output register through 1 to 3 serial interfaces and received and stored by the master processor. When the AD7656-1 uses a synchronous serial interface (SPI) to send data, it takes one unit of SCLK pulse time to send each bit of data, and it takes 96 SCLK pulses to send 16 bits of data from 6 channels. Multiple AD7656-1s in the daisy chain send data to the master processor in turn by relaying data. By using multiple serial interfaces to send data, the sending time can be reduced and the data transmission efficiency of the daisy chain can be improved. The relationship between the AD7656-1 serial data output interface and its corresponding channel data and the number of SCLK pulses required for sending are listed in Table 1.



　
2.2 Configuration of AD7656-1 Daisy Chain
　　
To work in daisy chain mode, AD7656-1 must set its data output to serial mode, and in serial mode, AD7656-1 must be configured to hardware mode. The so-called hardware mode is to determine the only working mode of AD7656-1 chip by fixed connection of device pins. At this time, AD7656-1 cannot be configured to software working mode. The main principles of AD7656-1 daisy chain configuration are as follows:
　　
① In multiple cascaded AD76561s, the chip at the farthest end of the cascade cannot be configured to daisy chain working mode, that is, its DCEN pin is set to low level (digital ground); but each AD7656-1 in the downstream data chain must be configured to daisy chain working mode, that is, the DCEN pin must be set to logic high level (VDRIVE).
　　
② SEL A, SEL B, SEL C enable DOUT A, DOUT B, DOUT C serial output ports accordingly. To select the DOUT X serial output port, set the corresponding SEL X to a logic high level, and the remaining unused SEL pins must be set to a logic low level. Figures 3 (a), (b), and (c) show the pin configurations of 1 to 3 serial output ports. ("NC" in the figure means not connected)

　　
③ The serial data input/output (DCIN X/DOUT X) of each AD7656-1 in the daisy chain must follow the same configuration, that is, there are as many DOUT outputs as there are DCIN inputs. [page]
　　
④ The CONVST X (X=A, B, C) of each AD7656-1 in the daisy chain must receive the CONVERT signal sent by the master processor, that is, the V1 to V6 channels of each AD7656-1 are configured to sample simultaneously.
　　
3 AD7656-1 daisy chain and S3C2410A interface design
　　
3.1 Hardware circuit design
　　
Two AD7656-1s are configured as a daisy chain to achieve 12 channels of simultaneous sampling. The data is output through the DOUT A port, and the S3C2410A receives the data using the synchronous serial interface 0 (SPIO), as shown in Figure 4. The GPE11 pin of the S3C2410A implements the MISO function of the on-chip synchronous serial interface SP10, the GPE13 (SCK) pin implements the synchronous clock output of the SPIO interface, the GPFO pin is configured as the interrupt EINTO input and connected to the BUSY pin of the AD7656-1 (1); the GPBO is set to PWM output, and the GPG9 pin is not set to a general output port, which is used as the control signal input of the CONVST and CS of the AD7656-1 (1) and AD7656-1 (2), respectively. When connecting AD7656-1 to peripheral circuits, the key pins must be set as follows: the DVCC, AVCC, VDRIVE, REFIN/OUT, and VSS pins of AD7656-1(1) and AD7656-1(2) must be connected in parallel with a 1 μF decoupling capacitor; in order to match the 3.3 V interface of S3C2410A, VDRIVE is connected to a +3 V power supply; STBY is connected to VDRIVE to select normal mode; RANGE is connected to ground to select an input range of ±10 V; H/S is connected to digital ground to select hardware configuration; SER/PAR is connected to VDRIVE, and RD is connected to digital ground to select serial mode. The DCEN of AD7656-1(1) is connected to VDRIVE, configured in daisy chain mode, and SEL A is connected to VDRIVE, SEL B, C, DCIN A, B, C are connected to digital ground; the DCEN of AD7656-1(2) is connected to digital ground, configured in non-daisy chain mode, and SEL A is connected to VDRIVE, SEL B, C, DCIN B, C are connected to digital ground. The specific configuration is shown in Figure 5.


　　
3.2 Data acquisition and transmission process
　　
The sampling interval of the signal is controlled by timer interrupt. The timer 0 of S3C2410A is set as the sampling timer and set to work in PWM mode. The PWM output TOUTO of timer 0 is used as the input of the analog-to-digital conversion control signal CON-VST of AD7656-1. The pin GPFO (EINTO) is set to fall edge trigger. The timing of A/D sampling operation is shown in Figure 6. When the sampling timer interrupt occurs, TOUTO (pin GPBO) outputs a high level and sends the CONVST signal to each AD7656-1 on the daisy chain to start analog-to-digital conversion. After 3μs, the data of the 12 channels are all converted, and the BUSY signal changes from high level to low level, triggering the EINTO interrupt and starting data transmission; GPG9 outputs a low level to the CS pins of AD7656-1 (1) and AD7656-1 (2), and the SPI channel 0 of S3C2410A starts to read data. After reading the conversion results of the 12 channels, GPG9 resumes high level output, TOUTO outputs a low level, and one sampling is completed. Wait for the next sampling timer interrupt to occur and perform the next sampling. The width TPH of the high level output of TOUTO can be controlled by setting the value of the internal register TC-MPBO of timer 0.

　　
AD7656-1 sends the collected data to S3C2410A through DOUT A, and its sending timing is shown in Figure 7. When BUSY returns from high level to low level, it means the conversion is over, triggering the external interrupt, EINTO, notifying S3C2410A to start SPI to receive data, and the CS signal becomes low level to start serial transmission. During the entire transmission process, CS remains at a low level until the transmission is completed.

　　
3.3 Software Design
　　
In the process of data acquisition of three-phase AC power, 256 points are required to be sampled in each cycle, that is, 256 points are sampled in 20 ms, that is, once every 78.125μs. S3C241OA timer O generates a timer interrupt every 78.125μs to start A/D conversion. After all the data of 12 channels are converted, the BUSY signal becomes low to trigger external interrupt 0, notifying S3C2410A to read data. S3C2410A outputs chip select signal CS to AD7656-1 and starts reading conversion results through SPIO. SPIO is configured as master input slave output (MISO) and MDA receiving mode. Since it only receives data, it needs to send dummy "OxFF" at the same time. After reading 12 channels of data, exit the interrupt, wait for the next timer to start the next conversion. After the 256-point data conversion is completed, pause the timing count and process the data. After completion, start the timing again to complete the next cycle of 256-point acquisition. The process is shown in Figure 8(a). It includes two interrupt subroutines: the sampling timer interrupt subroutine, which is used to start the sampling signal CONVST and set the external interrupt 0 to allow the response to the BUSY falling edge to trigger the interrupt, as shown in Figure 8(b); the external interrupt 0 (EINTO) subroutine, which is used to start SPIO to receive data, as shown in Figure 8(c).

　　
4 Conclusion
　　
This paper introduces the daisy chain working principle of the 16-bit analog-to-digital conversion chip AD7656-1, and designs a data acquisition interface based on the AD7656-1 daisy chain and S3C2410A, which can realize a 12-channel, high-precision ADC. SPI serial transmission has the characteristics of occupying less microprocessor I/O resources and simple hardware connection. When there are a large number of AD7656-1 chips in the daisy chain, in order to improve data transmission efficiency and meet real-time requirements, 2 or 3 serial ports can be used to transmit data. The main control processor can also use a DSP chip, which can also realize a daisy chain. This design scheme can be widely used in embedded systems such as power quality monitoring of power systems, substation protection and control IED, etc.