Detailed explanation of the working principle of P0 port of 51 single chip microcomputer

Three-state gate: Three-state gate buffer: 51 MCU P0 port input buffer

Output drive of P0 port: push-pull structure composed of two MOS tubes

When P0 port is used as IO line input state: ① read pin; ② read latch;

P0 port is used as address/data multiplexing port

When the P0 port is used as an IO line output, it can only output low level and high impedance state. An external pull-up resistor is required to change the high impedance state to output high level (compared with the push-pull output structure of the AVR microcontroller )

1. Structure and working principle of P0 port

The structure of one of the 8 bits of port P0 is shown in the figure below:

As can be seen from the figure above, the P0 port is composed of a latch, an input buffer, a switch, a NAND gate, an AND gate and a field effect transistor drive circuit. Looking at the right side of the figure, there is an icon labeled P0.X pin, which means that the P0.X pin can be any one of P0.0 to P0.7, that is, there are 8 circuits in the P0 port that are the same as the above figure.

Next, we will introduce each unit that makes up the P0 port:

Let's look at the input buffer first: There are two three-state buffers in the P0 port. When learning digital circuits, we already know that the three-state gate has three states, that is, its output can be high level, low level, and there is also a high impedance state (or forbidden state). Look at the picture above. The upper one is the buffer of the read latch. In other words, to read the data of the output end Q of the D latch, the three-state control end of the buffer of the read latch (labeled as "read latch" in the picture above) must be enabled. The lower one is the buffer of the read pin. To read the data on the P0.X pin, the control end of the three-state buffer labeled "read pin" must also be enabled, and the data on the pin will be transmitted to the internal data bus of our microcontroller.

D latch: To construct a latch, a sequential circuit is usually used. When we study digital circuits, we already know that a trigger can store a binary number (i.e., it has a holding function). In the 32 I/O lines of the 51 single-chip microcomputer, a D trigger is used to construct a latch. Look at the D latch in the figure above. The D terminal is the data input terminal, CP is the control terminal (i.e., the timing control signal input terminal), Q is the output terminal, and Q is the reverse output terminal.

For the D flip-flop, when there is an input signal at the D input terminal, if there is no signal at the control terminal CP (that is, the timing pulse has not arrived), the data at the input terminal D cannot be transmitted to the output terminal Q and the reverse output terminal Qnot. If the timing pulse of the timing control terminal CP arrives, the data input at the D terminal will be transmitted to the Q and Qnot terminals. After the data is transmitted, when the timing signal of the CP timing control terminal disappears, the output terminal will still maintain the data of the last input terminal D (that is, the last data is latched). If the next timing control pulse signal comes, the data at the D terminal will be transmitted to the Q terminal again, thereby changing the state of the Q terminal.

Multiplexer: In the 51 single-chip microcomputer, when the internal memory is sufficient (that is, when there is no need for external memory expansion, the memory mentioned here includes data memory and program memory), the P0 port can be used as a general input and output port (i.e. I/O). For the 8031 ​​single-chip microcomputer (without internal ROM) or the program written exceeds the internal memory capacity of the single-chip microcomputer, when external memory expansion is required, the P0 port is used as the "address/data" bus. Then this multiplexer is used to select whether to use it as a normal I/O port or as a "data/address" bus. Look at the picture above. When the multiplexer is connected to the bottom, the P0 port is used as a normal I/O port. When the multiplexer is connected to the top, the P0 port is used as an "address/data" bus.

Output drive part: As we can see from the above figure, the output of P0 port is a push-pull structure composed of two MOS tubes, that is, these two MOS tubes can only be turned on one at a time. When V1 is turned on, V2 is turned off, and when V2 is turned on, V1 is turned off.

AND gate, NAND gate: We have introduced the logical principles of these two unit circuits in the fourth lesson on digital and commonly used logic circuits. If you don’t understand, please go back to the fourth lesson and take a look.

We have previously explained in detail the various unit components of the P0 port. Now let’s study the specific working process of the P0 port when it is used as an I/O port and address/data bus.

1. Working principle when used as an I/O port

When the P0 port is used as an I/O port, the control signal of the multiplexer is 0 (low level). Looking at the line part in the figure above, the control signal of the multiplexer is connected to one of the input terminals of the AND gate at the same time. We know that the logical characteristic of the AND gate is "all 1s output 1, and 0s output 0". If the control signal is 0, the output of the AND gate is also a 0 (low level). When the output of the AND gate is 0, the V1 tube is cut off. When the control signal of the multiplexer is 0 (low level), the multiplexer is connected to the Q non-terminal of the latch (that is, the P0 port is used as an I/O port line).

The P0 port is used as an I/O port line, and its working process from the data bus to the pin output (i.e., output state Output) is as follows: when the write latch signal CP is valid, the signal of the data bus → the input terminal D of the latch → the reverse output Q non-terminal of the latch → the multiplexer → the gate of the V2 tube → the drain of V2 to the output terminal P0.X. As we have said before, when the control signal of the multiplexer is low level 0, the AND gate output is low level, and the V1 tube is cut off, so when used as an output port, P0 is an open drain output, similar to an OC gate. When driving a current load, an external pull-up resistor is required.

The figure below is the flow chart of data output from the internal data bus to the P0 port (red arrow).

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Port P0 is used as an I/O port line, and its working process of inputting from the pin to the internal data bus (i.e. input state Input) is as follows:

There are two situations when data is input (reading P0 port)

1. Read pin

To read the data on the chip pins and the pin number, the pin read buffer is turned on (that is, the control end of the three-state buffer must be valid) and input is made through the internal data bus. Please see the figure below (red header).

2. Read latch

The state of the latch output Q is read by opening the read latch tri-state buffer, see the figure below (red arrow):

In the input state, the signals read from the latch and the pin are generally consistent, but there are exceptions. For example, when a low level is output from the internal bus, the latch Q=0, Q=1, the field effect transistor T2 is turned on, and the port line is in a low level state. At this time, no matter whether the external signal on the port line is low or high, the signal read from the pin to the microcontroller is low, so the signal on the port pin cannot be read correctly. For another example, when a high level is output from the internal bus, the latch Q=1, Q=0, and the field effect transistor T2 is turned off. If the external pin signal is low, the signal read from the pin is different from the signal read from the latch. For this reason, the 8031 ​​microcontroller has the following agreement on the input operation of ports P0-P3: For this reason, the 8051 microcontroller has the following agreement on the input operation of ports P0-P3: For instructions belonging to the read-modify-write mode, the signal is read from the latch, and other instructions read the signal from the port pin line.

The characteristic of read-modify-write instruction is that the signal is input (read) from the port, calculated (modified) in the microcontroller, and then output (written) to the port. The following are some examples of read-modify-write instructions.

ANL P0,#immediate number;P0→immediate number P0

ENT P0,A ;P0→AP0

INC P1 ;P1+1→P1

DEC P3 ;P3-1→P3

CPL P2 ;P2→P2

The reason for this arrangement is that the read-modify-write instruction needs to obtain the original output state of the port, modify it and then output it. Reading the latch instead of the pin can avoid the original port state being read incorrectly due to external circuit reasons.

The P0 port is the bus port of the 8031 ​​microcontroller. It displays data D7-D0, low 8-bit address A7-AO, and tri-state in time. It is used to interface memory, external circuits, and external devices. The P0 port is the most widely used I/O port.

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2. Working principle when used as an address/data multiplexing port

When accessing external memory, port P0 is used as an address/data multiplexing port.

At this time, the 'control' signal of the multiplexer is '1', the 'AND gate' is unlocked, and the output signal level of the 'AND gate' is determined by the "address/data" line signal; the multiplexer is connected to the output end of the inverter, and the address signal is output via the "address/data" line → inverter → V2 field effect transistor gate → V2 drain.

For example: when the control signal is 1 and the address signal is "0", the AND gate outputs a low level, and the V1 tube is cut off; the inverter outputs a high level, the V2 tube is turned on, and the address signal of the output pin is a low level. Please see the figure below (the blue font is the level):

On the contrary, when the control signal is "1" and the address signal is "1", the output of the "AND gate" is high level, the V1 tube is turned on; the inverter outputs a low level, the V2 tube is turned off, and the address signal of the output pin is high level. Please see the figure below (the blue font is the level):

It can be seen that when outputting "address/data" information, V1 and V2 tubes are turned on alternately, and have a strong load capacity. They can be directly connected to the external memory without adding a bus driver.

Port P0 is also used as a data bus. When accessing external program memory, after port P0 outputs the lower 8 bits of address information, it will become a data bus to read the instruction code (input).

During instruction fetching, the "control" signal is "0", the V1 tube is turned off, and the multi-way switch also turns to the inverting output terminal Q of the latch; the CPU automatically writes 0FFH (11111111, that is, writes a high level '1' to the D latch) to the P0 port latch, turning off the V2 tube. Under the control of the read pin signal, the instruction code is read to the internal bus through the read pin tri-state gate circuit. See the figure below.

If the instruction is to output data, such as MOVX @DPTR, A (transfer the contents of the accumulator to the external RAM through the P0 port data bus), the multiplexer "control" signal is '1', the "AND gate" is unlocked, and the workflow is similar to the output address signal. The data is output from the "address/data" line → inverter → V2 field effect transistor gate → V2 drain.

If the instruction is to input data (read external data memory or program memory), such as MOVX A, @DPTR (input the content of a storage unit in the external RAM into accumulator A through the P0 port data bus), the input data is still transmitted to the internal bus through the read pin three-state buffer. The process is similar to the read instruction code flow chart in the figure above.

From the above analysis, we can see that when P0 is used as the address/data bus, before reading the instruction code or inputting data, the CPU automatically writes 0FFH to the P0 port latch, destroying the original state of the P0 port. Therefore, it can no longer be used as a general I/O port. Everyone must pay attention when designing the system in the future, that is, the program cannot contain instructions that use the P0 port as an operand (including source operands and destination operands).