Design of IC card reader/writer based on single chip microcomputer

1 Overview

C card is the abbreviation of Integrated Circuit Card. Some countries and regions call it Microchip Card or Microcircuit Card. The size of IC card is the same as that of magnetic card. It embeds integrated circuit on plastic card. The chip is generally a memory (ROM, EPROM.EPROM) that is not easy to lose data, a protection logic circuit, or a CPU. IC card was originally designed to solve the security problem in financial transactions. It brings a new transaction concept and huge advantages. Soon, this advantage was also noticed by other application departments, making it widely used in telephone, health care, road control and door lock control systems. As time goes by, the scope of application is still expanding, and the number of IC cards in use is growing exponentially. At the same time, in order to meet the needs of different application occasions, IC card manufacturers are still constantly launching new IC cards to the market. The price of IC cards will decrease year by year as the usage increases. All of these will undoubtedly greatly promote the popularization of IC cards in various fields. Wireless SOC development platform 499 yuan S3C44B0 ARM7 development board 378 yuan S3C2410 ARM9 development board 780 yuan AT91SAM7S64 ARM7
    According to the data exchange method between IC card and reader, IC card can be divided into contact IC card and contactless IC card. Contact IC card is an IC card that exchanges data by directly contacting the card's integrated circuit with the external interface device through tangible electrode contacts when in use. Contactless IC card communicates the data in the integrated circuit of the card with the external device interface device through radio waves or electromagnetic field induction. The card can read and write data without directly contacting the electrode of the interface device. According to the function and structure of IC card, IC card can be divided into storage IC card and smart IC card. Storage IC card is passive, and it can only realize various input/output of data. The internal circuit of this type of IC card can be divided into two major functional parts, data storage part and data encryption operation control part. And not all IC cards must have these two functions. We call IC card with only data storage function as non-encrypted memory card (Memory Card). IC cards with data storage functions and data encryption operation control are called encrypted memory cards (Memory Card with Security Logic). They have temporary or permanent data storage capabilities, and their contents can be used for processing or judgment. Smart IC cards are IC cards with microprocessor circuits in the integrated circuit of the IC card. It is an active IC card that can not only manage the I/O operations of various data, verify the personal password from the interface device, but also actively identify the interface device connected to it according to the requirements of the application system. Therefore, in the smart IC card, it is possible to establish authorizations for various application systems, store relevant data of multiple application systems, and achieve high reliability and high security control of data information storage, and can perform complex information processing and calculation. Universal memory IC cards are encapsulated by universal memory chips. Due to its simple structure and function, low production cost and easy use, they have been widely used in various fields. At present, the universal memory chips used for IC cards are mostly E2PROM, and their commonly used protocols are mainly two-wire serial connection protocol (I2C) and three-wire serial link protocol. Among them, the more commonly used are AT24 series chips produced by ATMEL. Take AT24C01 in this series as an example. It has a storage capacity of 1k, is suitable for low voltage/standard voltage operation of 2V~5V, and has the advantages of low power consumption and high reliability. Although AT89C2051 is a low-end model of ATMEL's 89 series microcontroller, it has 2k FLASH ROM (reprogrammable flash memory), 128×8-bit internal RAM and full static operation mode, and also has low power consumption and strong functions. The following takes AT24C2051 as an example to introduce the working principle and basic circuit connection of universal memory IC card. The circuit is simple, flexible to use, and can reliably read and write universal memory IC card. Since IC card use is mobile and global, it is particularly important to establish corresponding international and national standards. In the field of information technology, ISO (International Organization for Standardization) and IEC (International Electrotechnical Commission) jointly established a technical committee ISO/IEC JTC1 to formulate corresponding international standards. In the design of IC card application system, each link of IC card reading and writing control by reading and writing equipment should comply with the corresponding international standards to ensure the correct reading of data. This is the basis of IC card reader terminal design.

Design standards
Among these standards, the definition of chip and electrical characteristics and the requirements for operation timing are particularly important. Here, the electrical characteristics and timing of the synchronous card are introduced as an example. When using this card, the interface device puts all lines in state L, then VCC is powered on, Vpp is in idle state, CLK, RST and FCB are in state L, and the I/O of the interface device is placed in receive mode. The clock pulse is provided after t20 after the rising edge of VCC, and the duration of the clock pulse is t25. FCB remains in state L for at least t22 after the rising edge of the clock pulse. The first bit of data obtained on the I/O line can be regarded as a response, at which time CLK is in state L and is valid after t27, the falling edge of CLK. When FCB is in state H, each clock pulse is used to read the next data bit on the I/O line. In the reset response, the first clock pulse is given t24 after the rising edge of FCB. The duration of the clock pulse state H is t25, and the duration of state L is 1us (t26). The second and subsequent data bits are given at t27 after the clock is low and the CLK falling edge. The data bits are sampled sequentially with the rising edge of the clock pulse.

2 Hardware Features

2.1 Characteristics of AT24 Series Memory

AT24 series memory chips are manufactured using CMOS technology and have a built-in high-voltage pump, which can work under single voltage supply conditions. Its standard package is an 8-pin DIP package, and the functions of each pin are as follows:

SCL: Serial clock. At the rising edge of this pin, the system inputs data to each EEPROM device and outputs it at the falling edge.

SDA: Serial Data. This pin is open drain driven and can transmit data in both directions.

A0, A1, A2: Device/page addressing. Device address input terminals. In AT24C01/02, this pin is hard-wired.

Vcc: Generally input +5V operating voltage.

Figure 1 is a contact diagram of an IC card that complies with the ISO7816-2 standard. For the AT24 series universal memory IC card, only four contacts are usually used. The internal configuration of the AT24C01 is 128 8-bit bytes, and a 7-bit address is required for random word addressing.

2.2 Bus Status and Timing

The SCL and SDA buses of A24C01 can be pulled up to a high level through a resistor, and the data on SDA can only be changed periodically when SCL is at a low level. When SCL is at a high level, the change of SDA indicates the "start" and "stop" states. At this time, all addresses and data words are input and output from the EEPROM in 8-bit serial code.

Start state: When SCL is high, SDA changes from high to low. This command must be executed before other commands.

Stop state: When SCL is high, SDA changes from low to high. This command terminates all communications.

Confirmation: After receiving the data, the devices on the same bus confirm it by setting SDA to a low level.

2.3 Device Addressing

The AT24 series EEPROM requires an 8-bit device address immediately after the start state to perform read and write operations. The upper 4 bits of the device address code are 1, 0, 1, 0. For AT24C01/02, the three bits after the upper 4 bits of the address code are the device address code, corresponding to their hard-wired pins. The lowest bit should be the read and write selection bit, which can trigger a read operation when set to 0.

The specific format is as follows:

2.4 AT89C2051 chip

AT89C2051 is compatible with MCS-51 products. It has 2k FLASH ROM, 128 bytes ROM, 15 I/O pins, two 16-bit timers/counters, a five-vector two-level interrupt structure, a full-duplex serial port, a precision analog comparator, and an on-chip oscillator circuit and clock circuit. Its P1 port and P3 port are bidirectional I/O ports, of which P1.2~P1.7, P3.0~P3.5 and P3.7 have internal pull-up resistors. When AT89C2051 is used as an input terminal, "1" will be written to the pin first to turn off the internal MOS tube so that the pin is in a suspended state, thereby obtaining a high-impedance input.

FIG. 2 is a basic circuit connection diagram of a general-purpose memory IC card.

3 Read and write operation software

When the system uses a 6MHz crystal oscillator, the defined I/O lines and device addresses are as follows:

SCL BIT P1.7

SDA BIT P1.6

DEVICEAD_W DATA 10100000B ; Write card device address

DEVICEAD_R DATA 10100001B ; Card reader device address

3.1 Start Condition (START_IC)

In the start condition, when SCL is high, SDA changes from high to low. The procedure is as follows:

START_IC: CLR SCL; SDA is allowed to change only when SCL is low

NOP; add a null instruction delay to ensure signal reliability

NOP

SETB SDA

NOP

NOP

SETB SCL

NOP

NOP

CLR SDA

NOP

NOP

CLR SCL

NOP

RET[page]

3.2 Stop Condition (STOP_C)

In the stop condition, when SCL is high, SDA changes from low to high. The procedure is as follows:

STOP_IC:CLR SCL

NOP

NOP

CLR SDA

NOP

NOP

SETB SCL

NOP

NOP

SETB SDA

NOP

NOP

CLR SCL

NOP

NOP

CLR SDA

RET

3.3 Acknowledgement signal (ACK_IC)

When the receiver responds, the SDA level is pulled low after each byte is received. The procedure is as follows:

ACK_IC:CLR SCL

NOP

NOP

CLR SDA

NOP

NOP

SEIB SCL

NOP

NOP

CLR SCL

NOP

SETB SDA

NOP

RET

3.4 Write one byte of data to the IC card (WR_BYTE)

In the following program, parameter A represents the source data and R5 represents the number of bytes.

WR_BYTE: MOV R5, #08; one byte of 8-bit data

CLR SCL

NOP

NOP

WR_BYTE1: RLC A; left shift with carry, A.8->C

MOV SDA, C; Change the data on SDA when SCL is low

NOP

SETB SCL; pull up SCL to send data out

NOP

NOP

CLR SCL

NOP

NOP

DJNZ R5, WR_BYTE1; send 8 bits of data in A in sequence

SETB SDA

SETB SCL

JB SDA, $; Waiting for IC card confirmation signal

CLR SCL

NOP

RET

The main function of this subroutine is to sequentially shift the 8-bit data of one byte in A to the left according to the defined timing and transmit it through the pin. When one byte is sent, wait for the confirmation signal sent back by the IC card.

3.5 Read one byte from IC card (RD+BYTE)

The source program to read one byte from the IC card is as follows:

RD_BYTE: MOV R5, #08

SETB SDA; device SDA is in read state

CLR A ; Clear the A register

RD_BTYE1: MOV C, SDA; read one bit of data to the carry bit

RLC A; Left shift data to A.0

SETB SCL

NOP

NOP

CLR SCL

NOP

NOP

DJNZ R5, RD_BYTE1; read out 8 bits of data into A in sequence

RET ; No response signal

This program can be used to store the read data in A. It should be noted that the device that reads the data does not respond by confirming the status, but instead generates a stop status afterwards.

3.6 Byte write mode write data (WRITE_BYTE)

The parameters in the following program are: R6= =destination address, A= =data; the data is as follows:

WRITE_BYTE: PUSH ACC; save the data in A

LCALL START_IC ; send start signal

MOV A, #DEVICEAD_W; write device address

LCAL WR_BYTE[page]

MOV A, R6 ; write byte address

LCALL WR_BYTE

POP ACC; Restore data in A

LCALL WR_BYTE ；Write data

LCALL STOP_IC

RET

After receiving 8 bits of data, the EEPROM will send back a confirmation signal through SDA, and the transmitting device must terminate the write operation with a stop state. At this time, the EEPROM will enter a write cycle of the internal fixed memory and prohibit all inputs during this period, and will not respond to the communication until the write operation is completed. The write cycle can be customized, with a maximum of 10ms.

3.7 Write data in page write mode (WRITE_PAGE)

The parameters in the following program are P0= = source pointer, R6= = destination address, R7= = page length.

WRITE_PAGE: LCALL START_IC

MOV A, #DEVICEAD_W

LCALL WR_BYTE

MOV A, R6

LCALL WR_BYTE

WRITE_PAGE1: MOV A, @R0

LCALL WR_BYTE

INC R0

DJNZ R7, WRITE_PAGE1

LCALL STOP_IC

RET

AT24C01/02 can use the above program to write 8-byte pages. Its operation is similar to writing bytes. The difference is that it does not need to stop after the first byte is sent. After receiving the confirmation signal, it sends 7 bytes of data code and finally stops the page write sequence. The page of AT24C04/08/16 is 16 bytes.

3.8 Immediate Address Read Mode (READ_BYTEC)

The procedure for reading one byte of data in immediate address read mode is as follows: READ_BYTEC: LCALL START_IC

MOV A, #DEVICEAD_R

LCALL WR_BYTE

LCALL RD_BYTE ；Read the default address data

LCALL STOP_IC ；Send stop status response

RET

After the program is executed, its internal data word address pointer will remain at the last address accessed by the last read or write operation, and will increment by 1 and remain valid during the chip power-on period. Only when the address is at the end of the page will the next access scroll to the first address of the page.

3.9 Random Address Read Mode (READ_BYTER)

In the following program, R6 = = source address, the program is as follows:

READ_BYTER: LCALL START_IC

MOV A, #DEVICEAD_W ; Execute a null byte write sequence

LCALL WR_BYTE ; load data address

MOV A, R6

LCALL WR_BYTE

LCALL START_IC

MOV A, #DEVICEAD_R; immediate address read

LCALL WR_BYTE

LCALL DR_BYTE

LCALL STOP_IC

RET

The read mode requires a byte write sequence to load the data address. After the device and data address are written and acknowledged, another start condition is generated and the address of the read device is sent, stimulating an immediate address read.

3.10 Sequential Address Read (READ_BYTES)

In the following program: R0 = = destination pointer; R7 = = data length, the program is as follows:

READ+BYTES：LCALL START_IC

MOV A, #DEVICEAD_R

LCALL WR_BYTE

READ_BYTES2: LCALL RD_BYTE

MOV @R0, A; store data to the destination address

INC R0

DJNZ R7, READ_BYTES1

LCALL STOP_IC ；Stop after reading or writing the specified length

RET

READ_BYTES1: LCALL ACK_IC; send confirmation signal SJMP after receiving data READ_BYTES2

Sequential read is triggered by immediate address read or random address read, and sends a confirmation signal response after receiving one byte of data. When the reading device responds with a stop state, the operation is terminated. 4 Summary

The design system of the single-chip IC card reader is simple in structure, has high reliability in actual operation, and has certain scalability. It can be directly connected to the computer through the serial port of the single-chip computer after level conversion for data communication. In addition, it can also be connected to other pins or card holder contacts as needed. If the circuit and program are properly improved, encryption cards and CPU cards can also be read and written.