Program and debugging of driving AD9954 with C51 single chip microcomputer

When debugging, you must first correctly control SYNC_CLK, because this output pin is the 4th frequency of the internal DDS clock (assuming that the maximum DDS clock is 400MHz, then SYNC_CLK should output 100MHz; conversely, SYNC_CLK is usually used to infer the DDS system clock). The prerequisite is that bit1 (SYNC_CLK Disable) in Control Function Register No.1 (CFR1: 0x00) must be reset.

Then correctly set the REFCLK Multiplier and VCO Range in CFR2 according to the frequency of the input clock (0: 100~250MHz; 1: 250~400MHz). As long as there is nothing wrong with the external circuit, SYNC_CLK is generally OK.

I found that AD9954 is really good after using it. Not to mention the 400MHz system clock, I can actually use the control word Amplitude Scale Factor (ASF: 0x02) to adjust the amplitude of the output signal, provided that OSK Enable in CFR1 is turned on. And the 14-bit length can also achieve a high enough amplitude control accuracy. When it was used as a signal source, I also used an external AD835+TLV5638 to control the amplitude. Now I think it was really stupid.

In addition, the phase of the output signal is adjustable. The control word Phase Offset Word (POW0 0x05) contains a 14-bit phase offset control word, so the accuracy of phase adjustment is also quite high, up to 360°/16384 = 0.022°, which is definitely enough in most cases and much better than the 5-bit control word of AD9851 (360°/32 = 11.25°). See Program 1 for details.

Then I wanted to try the linear-sweeping mode, but I spent a whole day adjusting it and it didn’t work, so I went home for the holiday.

Recently, while working on my graduation project (Frequency Response Analyzer), I took out the original AD9954 test board for debugging. Of course, there was no problem with Single-Tone Mode. This time, I mainly studied Linear-Sweeping Mode again. So I opened the original program, looked at it for a while, and adjusted it for a while. Suddenly, I found an extremely simple error - a byte position of the control word was written wrong. I corrected it and tested it again, and everything was OK. See Program 2 for details. Last year, I spent a whole day to check it but couldn't find it. Wordless.

OK, now it's the last level - RAM mode. I read the relevant chapters of the datasheet again, and then wrote a program to try it out. The waveform was a mess. So I referred to the AD9954 sample code on the AD official website (ASM, see program 3 for details), and compared it with what I wrote step by step, and finally got it done. This is because when writing data to RAM, you only need to send the RAM instruction byte (RAM: 0x0b) once before the first data, see program 4 for details. But I didn't notice this, and sent 0x0b before each data, and the result was tragic. But in the end I found the reason, hehe!

The figure below is the switching time measurement waveform when the RAM Segment Address Ramp Rate is set to 0x0400 (1024). The time between the two cursors is about 10.24us, because 10.24us = 1024×10ns, it means the update rate is 10ns, that is, SYNC_CLK, which is the same as the fastest frequency update speed during linear sweep.

Logarithmic frequency sweep can be easily realized by using the RAM Mode of AD9954. You only need to calculate the corresponding logarithmic frequency points and store them in RAM.

In addition, AD9954 can also realize high-speed FM wave. If the fixed wave table has 1000 points, the frequency of the modulated wave can be 100kHz, 50kHz, 33.33kHz..., that is, 100/n kHz (n is a positive integer). If an indefinite wave table with 500~999 points is used, an FM wave with a frequency step of no more than 0.4% within 200kHz can be realized. However, it is a bit troublesome to realize, so AD9954 is generally not used as an FM wave signal source with continuously adjustable modulation wave frequency.

Now I have a good understanding of the programming part of AD9954. After the graduation project is completed, I will upgrade the signal source I made before when I have time. Remove AD835 and TLV5638 directly, add more basic FM/AM functions, and add an EEPROM for amplitude calibration storage. In addition, make a PCB for hardware circuit to reduce noise, and increase the output power of the power amplifier to 10Vpp@50 ohm load. [page]

The following is part of the program, shared with friends who are interested (it is just the beginning, please forgive me for the clumsiness):

Public program segment:

#include< reg51.h>
#include< absacc.h>
#include< intrins.h>
#define uchar unsigned char
sbit ioupdate = P1^0;
sbit sdio = P1^1;
sbit clk = P1^2;
sbit adcs = P1^3;
sbit adreset = P1^4;
sbit tlvcs = P1^5;
sbit ps0 = P1^6;
void send(uchar dat)
{
    flying i;
    for(i=0;i< 8;i++)
    {
        clk = 0;
        dat = _crol_(dat,1);
        sdio = dat&0x01;
        clk = 1;
    }
}
      Procedure 1: (Single-Tone Mode)
void main()
{
    P1 = 0xff;
    address = 0;
    adcs = 0;
    send(0x00);        //CFR1
    send(0x02);        //bit1 OSK Enable,bit0 Auto OSK Enable;
    send(0x00);
    send(0x00);
    send(0x42);        //bit6 comp PD,bit1 SYNC_clk Disable;SYNC_clk = DDSclk/4;
    ioupdate = 0;
    ioupdate = 1;
 
    send(0x01);         //CFR2
    send(0x00);         //not used;
    send(0x08);         //bit3 High Speed SYNC Enable;
send(0xa4);         //bit7-bit3 REF clk Multiplier factor;bit2 VCO Range  
                    //(0:100-250;1:250-400);bit1-bit0 Charge Pump;
    send(0x02);        //ASF,when OSK Enabled(CFR1 bit25);
    send(0x3f);
    send(0xff);
 
    send(0x04);        //FTW0  0x 00 a3 d7 0a=1MHz  (0x ff ff ff ff ==> 400MHz)
    send(0x00);
    send(0xa3);
    send(0xd7);
    send(0x0a);
 
    send(0x05);        //POW0，Phase Initial
    send(0x00);
    send(0x00);
    ioupdate = 0;
    ioupdate = 1;
    adcs = 1;
 
    adcs = 0;           //POW0.Phase shift 180 (0x 3f ff ==> 360)
    send(0x05);
    send(0x20);
    send(0x00);
    adcs = 1;
    ioupdate = 0;
ioupdate = 1;
}
      Program 2: (Linear-Sweeping Mode)
void main()
{
    P1 = 0xff;
    address = 0;
 
    adcs = 0;
    send(0x00);         //CFR1
    send(0x00);
    send(0x20);         //bit5 Linear Sweeping Enable
    send(0x00);
    send(0x46);         //bit2 Linear Sweeping No-Dwell
    ioupdate = 0;
ioupdate = 1;
 
    send(0x07);         //NLSCW
    send(0x10);
    send(0x00);
    send(0x00);
    send(0x00);
    send(0x10);
 
    send(0x08);        //PLSCW
    send(0x10);
    send(0x00);
    send(0x00);
    send(0x00);
    send(0x10);
 
    send(0x04);        //FTW0   0x 00 a3 d7 0a ==1MHz (0x ff ff ff ff ==> 400MHz)
    send(0x00);
    send(0xa3);
    send(0xd7);
    send(0x0a);
 
    send(0x06);        //FTW1  0x 01 68 72 b0 ==2.2MHz (0x ff ff ff ff ==> 400MHz))
    send(0x01);
    send(0x68);
    send(0x72);
    send(0xb0);
    adcs = 1;
    ioupdate = 0;
    ioupdate = 1;
 
    ps0 = ~ps0;        //Toggle ps0 to sweep;
    ps0 = ~ps0;
}
      Program 3: (AD9954_ADIcode)

      Procedure 4: (RAM Mode)
void main()
{
    P1 = 0xff;
    ps0 = 0;
    address = 0;
    adcs = 0;
    send(0x01);       //CFR2
    send(0x00);       //not used;
    send(0x00);       //bit3 High Speed SYNC Enable;
    send(0xa4);       //bit7-bit3 REF clk Multiplier factor; bit1-bit0 Charge Pump;
 
    send(0x04);       //FTW0;
    send(0x12);
    send(0xf6);
    send(0x84);
    send(0xbe);
    ioupdate = 0;
    ioupdate = 1;
 
    send(0x00);       //CFR1
    send(0x80);       // bit7 RAM Enable;bit5-3 Internal Profile Control
    send(0x00);
    send(0x02);        //bit1 SDIO Only;
    send(0x00);        //bit6 comp PD,bit1 SYNC_clk Disable;SYNC_clk = DDSclk/4;
 
    send(0x02);        //ASF,when OSK Enabled(CFR1 bit25);
    send(0x3f);
    send(0xff);
    ioupdate = 0;
    ioupdate = 1;
 
    send(0x07);        //RSCW0;ps0 = 0; ps1 = 0;
    send(0xff);         //RAM Segment Address Ramp Rate< 7:0>
    send(0xff);         //RAM Segment Address Ramp Rate< 15:8>
    send(0x07);
    send(0x00);        //Segment0 Address:0x00000-0x00007
    send(0x00);        //RSCW0
 
    send(0x08);        //RSCW1;ps0 = 1; ps1 = 0;
    send(0xff);         //RAM Segment Address Ramp Rate< 7:0>
    send(0xff);         //RAM Segment Address Ramp Rate< 15:8>
    send(0x00);
    send(0x01);        //Segment1 Address:0x00000-0x00001
    send(0x04);
    adcs = 1;
    ioupdate = 0;
    ioupdate = 1;
 
    adcs = 0;
    send(0x0b);        //RAM
    send(0x00);        //stall freq into RAM from the final address to beginning address;
    send(0xa3);
    send(0xd7);
    send(0x0a);                  //RAM0     1MHz
 
    send(0x00);
    send(0xf5);
    send(0xc2);
    send(0x8f);                   //RAM1      1.5MHz
 
    send(0x01);
    send(0x47);
    send(0xae);
    send(0x14);                   //RAM2       2MHz
 
    send(0x01);
    send(0x99);
    send(0x99);
    send(0x99);                   //RAM3       2.5MHz
 
    send(0x01);
    send(0xeb);
    send(0x85);
    send(0x1e);                   //RAM4       3MHz
 
    send(0x02);
    send(0x3d);
    send(0x70);
    send(0xa3);                   //RAM5       3.5MHz
 
    send(0x02);
    send(0x8f);
    send(0x5c);
    send(0x28);                   //RAM6       4MHz
 
    send(0x02);
    send(0xe1);
    send(0x47);
    send(0xae);                   //RAM7       4.5MHz
 
    ps0 = 1;
    send(0x0b);         //RAM Instruction Again
    send(0x03);
    send(0x33);
    send(0x33);
    send(0x33);                   //RAM0       5MHz
 
    ioupdate = 0;
    ioupdate = 1;
 
    send(0x07);         //RSCW0;ps0 = 0; ps1 = 0;
    send(0x00);         //RAM Segment Address Ramp Rate< 7:0>
    send(0x04);         //RAM Segment Address Ramp Rate< 15:8>
    send(0x07);
    send(0x00);
    send(0x60);         //RAM Mode of Operation: Continuous Bidirectional Ramp
    adcs = 1;            //RSCW0
    ioupdate = 0;
    ioupdate = 1;
}