Works at 2.4 GHz ISM. The frequency band has 400 million available address codes, which can be used simultaneously in the same place without cross-frequency through frequency hopping addressing technology. The bandwidth of the transmitted signal is greater than the minimum bandwidth required for the transmitted information, and the bandwidth is widened through the expansion function, which has nothing to do with the transmitted information data, and is only known by the transmitter and receiver. At the receiving end, the same spread spectrum code is used for correlation demodulation to despread and restore the transmitted information data. Data is carried by all frequency hopping points. If noise does not affect all frequency hopping points, information can be repaired. Under certain conditions, multiple systems can coexist in the same frequency range. This paper introduces the design of a wireless intelligent frequency hopping digital loudspeaker developed using ATmega8 MCU and nRF24L01 RF transceiver. By using intelligent frequency hopping addressing technology, the transmitter can be automatically identified by the receiver more quickly. Any transmitter can match any receiver. After matching, it will automatically lock until the transmitter is turned off or leaves the radio coverage. Under the condition of straight-line transmission without obstacles, the output power is 5 W, and the effective distance of transmission and reception is ≤60 m.
1 System Analysis and Design
The system consists of MCU, transmission and receiving systems. The audio signal is amplified by the front-end signal processing circuit of the transmitter and sent to the A/D inside the MCU for sampling. The MCU packages the sampled data and sends it out through the RF module. The receiving MCU reads the data packet from the RF module and sends it to the TIMER1 inside the MCU for PWM modulation, and then outputs it to the external low-pass filter, and finally restores the corresponding audio signal. The system principle is shown in Figure 1.
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1.1 Main control MCU module
The MCU uses the AVR series ATmega8, which is a low-power 8-bit CMOS microcontroller based on the enhanced AVR RISC structure. Due to its advanced instruction set and single clock cycle instruction execution time, the data throughput of ATmega8 reaches 1 MIPS/MHz, and the performance reaches 16 MIPS at 16 MHz, which can alleviate the contradiction between power consumption and processing speed of the system. The operating voltage is 2.7~5.5 V, and it integrates 8-way 10-bit ADC, SPI serial interface, 16-bit timer with PWM modulation output, and 512 Byte EEPROM. Its internal resources can meet the requirements of the transmitter and receiver MCUs.
1.2 RF module
nRF24L01 is a new single-chip RF transceiver device that works in the 2.4~2.5 cHz ISM frequency band. It has built-in frequency synthesizer, power amplifier, crystal oscillator, modulator and other functional modules, and integrates enhanced ShockBurst technology, in which the output power and communication channel can be configured through the program. Address and CRC check functions can be performed. nRF24L01 has low power consumption. When transmitting at a power of -6 dBm, the working current is 9 mA; when receiving, the working current is 12.3 mA. Multiple low-power working modes make energy-saving design more convenient. The carrier of the transmission signal of the sender and receiver changes discretely according to a predetermined rule to avoid interference and complete the transmission. In short, the frequency hopping technology FHSS does not suppress interference but tolerates interference. Because the carrier frequency is hopping, it has the ability to resist high-frequency and partial bandwidth interference. When the number of hopping frequencies is large enough and the frequency hopping bandwidth is wide enough, its anti-interference ability is strong. The rapid hopping of the carrier frequency has the effect of frequency diversity, so that the system has the ability to resist multipath fading. The orthogonality of the frequency hopping pattern can be used to form a frequency hopping code division multiple access system, share spectrum resources, and have the ability to withstand overload.
1.3 Audio Amplification
As shown in Figure 2, the circuit U5A, R8, C17, R7, R14, R9, R16, and R13 are responsible for amplifying the microphone input signal with an amplification factor of 10 times. R8 provides a DC bias to the microphone, which is coupled to the op amp U5A through C17. R7, R14, and R9 are used to provide a virtual ground for the op amp. If a 3.5 mm audio signal connector is inserted into J5, the subsequent circuit will disconnect from the preamplifier, thereby switching between the MIC sound and the external audio input. U5B, R11, R15, R17, R19, and C21 are responsible for amplifying the input MIC and external audio signals, with an amplification factor of 5 times, and the principle is similar to that of the preamplifier. The op amp uses LMV358, which is a Rail to Rail dual op amp with an operating voltage of 2.7 to 5 V, a gain-bandwidth product of 1 MHz, and an operating current of 140 μA, which is suitable for battery power supply.
1.4 Power supply voltage regulation
LDO uses PAM3101, which is a series of positive linear regulators. Its features are low quiescent current and low voltage drop, making it an ideal choice for battery-powered applications. The small SOT--23 and SOT-89 packages are attractive for portable and transmitting devices. Thermal shutdown and current limiting prevent device failure in extreme working environments.
2 System interface design
2.1 Transmitter system interface
As shown in Figure 3, ATmega8 is connected to NRF24L01 via SPI. Before initializing NRF24L01, the IO port must be initialized, and the direction register DDR is set as shown in the arrow in the figure. The operating frequency of ATmega8 is 16 MHz, so by setting the SPCR and SPSR registers to make SPI work in clock doubling mode, the SPI clock frequency can reach 8 MHz. The internal A/D working clock is 250 kHz after 64 division; the single conversion cycle is 52μs; in continuous conversion mode, the sampling frequency is about 20 kHz and 8 bit accuracy. The ADC interrupt will be triggered after each conversion is completed. The power supply is an important part of the circuit, and its performance directly affects the output sound quality. Since the instantaneous current of the transmitter RF module is large when it is in the transmitting state, if the analog device and the RF module use the same LDO, the output audio will be seriously disturbed. Therefore, the analog device and the digital device each use independent LDO to minimize the impact.
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2.2 Receiver System Interface
As shown in Figure 4, the connection method between ATmega8 and NRF24L01 is the same as that of the transmitter, and the IO direction setting is also the same. In order to prevent power fluctuations caused by NRF24L01 returning ACK, analog devices and digital devices use independent LDOs. Since ATmega8 has fewer IO ports, several internal hardware interfaces use the same IO, resulting in interface conflicts. SPI's MOSI and Timer2's OC2 share PB3, SS and Timer1's OC1B share PB2, and finally only the 16-bit Timer1OC1A can be used. By modifying the TCCR1A register, Timer1 can work in 8-bit PWM mode with an operating frequency of 62.5 kHz. Modifying OCR1 can change the PWM duty cycle output on OC1B. Timer2 works in compare match mode, interrupts once every 52μs, and modifies the data in the buffer to send it to Timer1, allowing it to change the PWM duty cycle. After filtering out the PWM high-frequency components through a low-pass filter, an audio signal is finally obtained.
3 Main control software flow
3.1 Transmitter software flow
After the MCU is powered on and reset, the SPI interface will be initialized first, and then the IO settings will be performed. Then the peripherals NRF24L01 and Timer0 will be initialized. After completing the initialization of NRF24L01, the search for the receiver will follow. A brief algorithm is attached in the flowchart. After establishing a handshake with the receiver, the A/D will be initialized, and the audio signal will be sampled, and the data will be saved in the A and B buffers. Once the A buffer overflows, the newly sampled data will be transferred to the B buffer, and the data in the A buffer will be packaged and sent. Then it will enter the receiving mode and wait for the receiving end to return ACK. At the same time, the collected data will be saved in the B buffer. When ACK is received, it will enter the next cycle. If data is continuously sent within 10 minutes and no ACK is received, it is considered that the connection with the receiving end has been interrupted, and it will enter the standby state. The timer triggers an interrupt every 10 ms, and the current connection status is displayed through the red and green LEDs. In normal state, the green LED is always on. Once packet loss occurs, only the red LED is always on, which is used to inform that the distance between the transmitter and the receiver is too far or the signal is blocked or interfered by obstacles.
3.2 Software flow of the receiver
The software implementation flow of the receiver is the reverse process of the transmitter. First, initialize the IO, SPI, timer, and NRF24L01 of ATmage8, and its settings are consistent with the transmitter. Then set NRF24L01 to the receiving state. The MCU will search for the transmitter handshake signal and idle channel. If the handshake signal cannot be found, it will wait on the idle channel to actively search for the channel. After completing the signal handshake, the receiver will wait for the transmitter to send a data packet and move the data in the data packet to the buffer. If no data packet is received after 10 minutes, it will enter the standby state. Timer2 works
In the comparison match mode, once TNCT2 is equal to OCR2, the MCU will clear the TNCT2 hardware, thereby generating a comparison match interrupt with a period of 52μs, and use this interrupt to read the audio data from the buffer to Timer1 for outputting the PWM duty cycle. At the same time, the timer will also generate a 10 ms interrupt for the LED to display the connection status, and the implementation principle is consistent with the transmitter.
4 Performance test
The wireless intelligent frequency hopping digital amplifier realizes digital transmission with a radio frequency of 2.4 to 2.5 CHz. Under the condition of unobstructed straight-line transmission, the effective distance is 60 m. The transceiver and transmitter can automatically answer and retransmit. The frequency response is 100 Hz to 10 kHz. The signal-to-noise ratio is >45 dB. It automatically hops in 125 optional working channels, and the channel switching time is extremely short. The maximum current of the transmitter in the working state is 12 mA, the maximum current in the standby state is 0.06 mA, the output power is 5 W, and the data rate is 2 Mbit·s-1.
5 Conclusion
The design scheme of the wireless intelligent frequency hopping digital amplifier is developed using ATmega8 MCU and nRF24L01 RF transceiver device, as well as intelligent frequency hopping inquiry technology. It automatically hops in the optional working channels, and the channel switching time is extremely short. Under the condition of unobstructed straight-line transmission, the output power is 5 W and the effective transmission and reception distance is within 60 m. Although the application of ATmega8 MCU reduces the cost of the loudspeaker, the performance limitation of ATmega8 MCU causes the sound amplification effect to have audio popping phenomenon. There are many processing methods, including narrow-band high-frequency and intermediate-frequency frequency selection filtering, plus a digital noise suppression circuit to effectively avoid pulse noise, and multiple enhancements to the main sound source to minimize background noise and improve the sound transmission quality.
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