CC1101/CC1100, STC MCU simulation 2262-2272 decoding

In the past few days, I have studied the common wireless remote control switches on the market. Their wireless parts are mostly implemented with 2262-2272 encoding. I looked for some information on 2262-2272 soft decoding on the Internet, but found that there is very little information, and even if there is information, it is not very practical. So I wrote this blog.

The frequency calculation formula of 22262 is F=32000/Ros (KΩ) KHz, where Ros is the oscillation resistance. It takes 32 clock cycles to send one bit, and the start bit takes 128 clock cycles. The encoding format of 2262 is as follows:

'F' is only available when the address is 0, and the data bit is only '0' or '1'.

The connection between cc1101 and stc microcontroller is as follows:

ＳＩ－Ｐ１．５；

ＳＯ－Ｐ１．６；

ＣＬＫ－Ｐ１．７；

ＣＳ－Ｐ３．４；

ＧＤＯ０－Ｐ４．２（ＣＣＰ０）；

ＧＤＯ２－Ｐ４．３（ＣＣＰ１）；

The configuration of cc1101 is as follows:

    0x08,//0x0B,   // FSCTRL1   Frequency synthesizer control. 
    0x00,   // FSCTRL0   Frequency synthesizer control. 
    0x0c,   // FREQ2     Frequency control word, high byte. 
    0x1d,//0xAA,//,   // FREQ1     Frequency control word, middle byte. 
    0x89,//0x55,//   // FREQ0     Frequency control word, low byte. 
    0xc6,//0x8A,   //2d MDMCFG4   Modem configuration. 
    0x45,//0x01,   //3B MDMCFG3   Modem configuration. 
    0xb2,//0x73,   // MDMCFG2   Modem configuration. 
    0x02,//0xA2,   // 22  MDMCFG1   Modem configuration. 
    0xF8,   // MDMCFG0   Modem configuration.

    0x00,   // CHANNR    Channel number. 
    0x40,//0x00,   // DEVIATN   Modem deviation setting 

(when FSK modulation is enabled). 
    0x56,//0xB6,   // FREND1    Front end RX configuration. 
    0x11,   //10 FREND0    Front end RX configuration. 
    0x18,   // MCSM0     Main Radio Control State Machine configuration. 
        0x00, 
    //0x0f,        //MCSM1 
    //0x30, 
    0x16,//0x1D,   // FOCCFG    Frequency Offset Compensation Configuration. 
    0x6c,//0x1C,   // BSCFG     Bit synchronization Configuration. 
    0x43,//0xC7,   // AGCCTRL2  AGC control. 
    0x40,//0x00,   // AGCCTRL1  AGC control. 
    0x93,//0xB2,   // AGCCTRL0  AGC control.

    0xe9,//0xEA,   // FSCAL3    Frequency synthesizer calibration. 
    0x2A,//0x0A,   // FSCAL2    Frequency synthesizer calibration. 
    0x00,   // FSCAL1    Frequency synthesizer calibration. 
    0x1f,   // FSCAL0    Frequency synthesizer calibration. 
    0x59,   // FSTEST    Frequency synthesizer calibration. 
    0x81,//0x88,   // TEST2     Various test settings. 
    0x35,//0x31,   // TEST1     Various test settings. 
    0x09,   // TEST0     Various test settings. 
    0x09,   // IOCFG2    GDO2 output pin configuration. 
    0x4d,   // IOCFG0D   GDO0 output pin configuration. 

Refer to SmartRF?Studio User Manual for detailed pseudo register explanation.

    0x00,   // PKTCTRL1  Packet automation control. 
    0x30,   // 05   PKTCTRL0  Packet automation control. 
    0x00,   // ADDR      Device address. 
    0x2e,   // PKTLEN    Packet length.

The asynchronous receiving speed is configured to be about 2.1K here. According to the CC1101 manual, during asynchronous reception, the error of its sending frequency should be within 1/8 of the set receiving frequency. Tests have shown that this setting can fully accept the 2262 encoding with an oscillation resistor of 475.

There is one thing I want to explain here. I haven't found out the reason. When cc1101 receives 2262 code, the first start bit and the first data level cannot be received, and about 132-140 oscillation cycles will be lost. This can be seen on an oscilloscope using a cc1101 and a super-regenerative receiving module to receive the same data. However, it does not affect data reception because generally 2262 code will be sent at least 4 times.

GDO0 is data output when receiving and is automatically configured as data input when sending. The rising and falling edge capture of ccp0 of STC is turned on, and ccp0 jumps to P4.2.

The key to 2262 soft decoding is to find the correct start bit. Use timer 0 resources, configured as a 16-bit up counter, with an initial value of 0x0000. The process is as follows: When ccp0 captures the rising edge for the first time, start the timer count, when it captures the falling edge, stop the timer and record the counts of TH0 and TL0 at this time and restart the timer, when it captures the rising edge again, stop the timer and record the values ​​of TH0 and TL0 and restart the timer, at this time, a high level and a low level width have been read, and then compare to see if the low level width is 30-33 times the high level width. If it is, it can be considered as the start bit of the 2262 code. If not, it will be repeated until the right ratio is found.

After finding the start bit, capture in a loop and capture at least two 2262 encoding cycles. Because the OOK/ASK method is too unstable, two decoding comparisons are performed and only if they are the same can they be considered correct.

Assuming that the capture is complete, it is time for the decoding process. Note that the 2262 encoding rule requires four level widths to represent each bit. In fact, it doesn’t matter whether it is a high level or a low level. You only need to pay attention to the ratio rule of the four levels:

‘0’1:3,1:3

‘1’3:1,3:1

‘F’1:3,3:1

It should also be noted that in 2262 encoding, 'F' can only appear in the address code. If 'F' appears in the data code, it can be considered a decoding error.