Design of hierarchical distributed management system based on DSP chip

1 Overview

1.1 Background

Digital signal processors (DSPs) are generally used to run core data processing algorithms, but in some special environments, DSPs must be used to manage the core chip of the control unit. This paper presents a hierarchical distributed image processing system, in which the core chip of the management computer is AD's floating-point DSP (ADSP21020). It not only undertakes the management and control tasks of the image processing system, but also must respond to and execute key instructions from the upper 1553 bus in real time. This paper focuses on the coordinated control of the two-level distributed system by the management computer based on the DSP chip.

1.2 System Introduction

This image processing system is a distributed computer system, which consists of 5 modules, including preprocessing unit, mass storage, offline data parallel processing unit, communication unit and management computer. The management computer is the control core of this system, which manages the internal system through RS485 bus and communicates with the upper system through 1553 bus. The internal control functions of the management computer are divided into two categories: real-time control and non-real-time control. Real-time control is for tasks with strict timing requirements and real-time response. The management computer provides control pulses to the CCD detector and communication unit through the exclusive RS422 serial bus. Non-real-time control is for signals that do not require time accuracy and can even be interrupted by other programs, that is, the serial bus RS485 that transmits instructions and data. As the control core, the management computer exchanges data with other units through it to query the health status.

The key to the design of the management computer lies in the coordination between the two-level distributed systems, including the parallel management of the RS485 bus and the 1553 bus, and the switching between the two working modes of accepting external control and managing internal units. The two-level distributed system is shown in Figure 1. This article mainly discusses this part.

2 Design of management computers

2.1 Analysis of computer management tasks

The management computer has two working modes: 1. Receive 1553 bus instructions and data; 2. Manage and control the internal units of the image processing system. The information sent by the 1553 bus mainly includes the type of processing task, working time, working times, status detection, etc. The internal management tasks of the management computer include the transmission of relevant image public information, such as image generation time and location, etc., as well as health status detection. The priority of the management computer receiving 1553 bus instructions and data is obviously higher than the internal management work. Under normal circumstances, the management computer is always in the internal management work state, so when a command is sent from the 1553 bus, it must interrupt its internal management work, save the working state, and respond to the command of the upper layer 1553 bus. [page]

There are two different ways to interrupt the management computer of the 1553 bus: precise interruption and imprecise interruption. Precise interruption means that no matter what the management computer is doing, it must be stopped immediately. Imprecise interruption means that you must wait for the management computer to complete the communication task before responding to the 1553 bus interruption. Considering that the commands sent by the 1553 bus do not have very strict time requirements and considering the complexity of the design, the second strategy, i.e. imprecise interruption, is adopted in the image processing system.

Since the design uses imprecise interrupts, the commands sent by the 1553 bus cannot be responded to in time, and a buffer strategy must be used. Here, a FIFO dual-port memory with a first-in-first-out function is used. It can automatically receive and temporarily store data from the 1553 bus, and the management computer also sends data to the 1553 bus through the FIFO.

The functional block diagram of the management computer unit is shown in Figure 2. 2.2 1553 bus interface design

The interface between the 1553 bus RT board and the management computer is realized through a shared dual-port FIFO buffer memory. The FIFO uses a CY7C439 bidirectional memory.

The 1553 bus interface design is shown in Figure 3.

2.3 RS485 interface design

The RS485 interface is implemented by the parallel-to-serial conversion chip TL16C550 and the RS485 driver receiver MAX489, as shown in Figure 4.

2.4 Coordination between 1553 bus and RS485 bus

The program for managing the computer consists of three parts: 1553 bus communication program, RS485 communication program and RS485 state saving program. Their communication methods are all through interruption. The 1553 bus communication program is implemented through the interruption method of FIFO, while the RS485 bus communication program responds to the interruption of TL16C550. DSP has four user interrupt lines. Since the priority of 1553 bus interrupt is higher than that of RS485 bus, the interrupt vector 1553 bus is set at a higher priority part inside DSP. The program control flow is shown in Figure 5. [page]

3 Principle Prototype Debugging Results

3.1 RS485 bus debugging

The RS485 bus communication protocol uses NRM (Normal Response Mode). Other units in the system cannot send information directly to the management computer. The management computer must send commands and they must respond to commands. The communication between the controlled units must be carried out through the management computer. The corresponding data transmission includes image time, image area, instrument working status (temperature, pressure, etc.), and working mode. The data frame format is as follows:

Control word: instruction, data identifier.

Test results:

① All kinds of data are received correctly;

② The recipient can start the self-check procedure and return the corresponding information.

3.2 1553 bus interface debugging

The FIFO interrupt line is connected to the highest priority INTR0 of the DSP. The management computer acts as the RT of the 1553 bus and interprets and executes 1553 standard frame format instructions.

Test results:

① When the management computer is idle, it can respond to the 1553 bus interrupt in time;

②When the management computer sends information to RS485, it can correctly respond to the 1553 bus interruption;

③When the management computer receives RS485 information, the sender cannot know the interrupt status and still continues to send. The solution is that after the interrupt returns, the management computer sends a command to the device to request retransmission. Conclusion

This paper discusses the design of a management system based on DSP, focusing on the coordination between two-level distributed systems. If precise interrupts are used on the 1553 bus interrupt, the program will be very complicated, but it will be of great benefit to the real-time control system. Since the real-time nature of the high-level commands of this system is not very strong, it is sufficient to use non-precise interrupts.