Abnormal Interrupt Technology in ARM S3C4510B System

Introduction

As people's requirements for electronic products become higher and higher, 8-bit processor systems represented by the 80C51 series are beginning to face more and more limitations and challenges, and people's calls for high-performance chips and embedded functions are also getting higher and higher. 16/32-bit processor systems have received unprecedented attention and importance. The 32-bit ARM system series processors are one of the representatives. The S3C4510B processor is a 16/32-bit RISC processor based on the ARM7 system, with 8KB of CACHE/SDRAM integrated internally, an embedded EARTHNET controller, 7 processor modes and a processor structure with internal multi-threading and external multi-processors. The abnormal interrupt technology, which is of great significance in embedded systems, also reflects some unique characteristics of the ARM system in the S3C4510B system. Based on the characteristics of the S3C4510B system, this paper analyzes the functions and characteristics of the seven abnormal interrupts in the system. And gives the application example code of SWI abnormal interrupt (external interrupt) and IRQ abnormal interrupt (software interrupt).

1 Abnormal Interrupts in S3C4510B System

1.1 Characteristics of Abnormal Interrupts

in S3C4510B System There are usually three ways to control the execution flow of programs in S3C4510B system. The first is the normal program execution process, that is, increasing the program counter PC according to the instruction type to make the program execute sequentially; the second is to control the execution of the program by jumping, which can be performed by using the jump command, or by directly modifying the program counter to achieve the purpose of jumping; the third is the abnormal interrupt method, which can realize the processing of internal and external abnormalities, the call of system functions and the control of program processes according to the execution of the software, the abnormal request of the external device, etc.

The abnormal interrupt of the S3C4510B system has the following characteristics. First, as a component of the ARM system RTOS (real-time operating system), the abnormal interrupt in the program must convert the processor mode according to the requirements of the ARM system. Secondly, if there is a need for system optimization, the conversion between 32-bit ARM processing instructions and 16-bit THUMB instructions can be performed. In addition, when the S3C4510B processor is running normally, the return address is saved by storing the PC in the LR register. Since the value of the counter PC when the interrupt occurs has sometimes been updated, such as when an external interrupt and a fast interrupt occur; sometimes it may not be updated, such as when a software interrupt and an undefined instruction abort occur, the return address must be corrected by software according to the actual situation before it can return correctly. Finally, it should be noted that the ARM system supports mutual calls between C language and assembly language programs, and is coordinated by ATPCS rules, so the exception interrupt handler must perform register processing according to ATPCS rules.


1.2 Types of exception interrupts in the S3C4510B system

S3C4510B has seven different types of exception interrupts, which are adapted to different interrupt needs. According to the characteristics of the ARM series processors, various exception interrupts correspond to different working modes of the ARM series. Their types and corresponding relationships are shown in Table 1. Among

them, the reset interrupt is the highest priority interrupt. Under the premise that the reset pin is valid, the reset interrupt will be caused when the system is powered on or reset. Data access abort occurs when the target address of the data access instruction does not exist or the address does not allow the current instruction to access. The instruction prefetch abort interrupt is when the processor or system coprocessor considers the current instruction to be undefined. When the system prefetches the instruction, this interrupt is executed. The undefined abort is generated when the processor or system coprocessor considers the current instruction to be undefined. Therefore, floating-point vector operations can be simulated according to this abnormal interrupt mechanism. Fast interrupts and external interrupts are generated when the corresponding interrupt request pin is valid and the corresponding interrupt disable flag in the status register is cleared. Among them, the external interrupt can also be used to switch between various system processes; the soft interrupt is defined by the user and called by the SWI instruction when the program is running. It can be used for programs in user mode to call privileged mode instructions. In the RTOS system, the system function call can be implemented through this interrupt mechanism.

1.3 S3C4510B system response to abnormal interrupt

The response process of the S3C4510B system to abnormal interrupt is as follows:

(1) Save the value of the processor's current status register CPSR, interrupt mask and various condition flags to the SPSR of the abnormal interrupt to be executed. Electronic circuit diagram
(2) Set the value of the current program status register CPSR. These include: setting the value of the corresponding bit of CPSR to make the processor enter a specific processor mode; masking interrupts as required, usually IRQ interrupts should be masked, and FIQ interrupts should be masked when there is a FIQ interrupt.

(3) Set the Lr register. Set the value of the Lr register of the interrupt corresponding mode to the return address of the abnormal interrupt.
(4) Process the program counter PC. Set the PC value to the address of the corresponding interrupt vector, so as to jump to execute the interrupt program. [page]

After the processor executes the above process, the processor has entered the abnormal interrupt processing state from the interrupt vector. After the abnormal interrupt is processed, at the end of the abnormal interrupt program, the processor enters the return state of the abnormal interrupt. The process is as follows:

(1) Restore the status register. Assign the SPSR value saved in the interrupt mode to the current status register.

(2) Copy the return address to the program counter. In this way, the program will return to the next instruction generated by the abnormal interrupt or the instruction where the problem occurs.

The entire response and return process is shown in Figure 1.

It should be noted that for different abnormal interrupts, the calculation method of the return address is also different. When IRQ and FIQ exception interrupts occur, the program counter PC has been updated, while SWI interrupts and undefined instruction interrupts are generated by the current instruction itself, and the program counter PC has not been updated, so the address of the next instruction must be calculated to perform the return operation; instruction prefetch abort exception interrupts and data access exception interrupts require returning to the execution site where the exception occurred and re-executing the operation.


2 Installation of exception interrupt handlers in the S3C4510B system

The S3C4510B system installs the exception interrupt handler through the exception vector table, that is, the exception vector table points to the entry of the exception interrupt handler to realize the jump for the exception interrupt. Here we need to introduce the interrupt vector table of the S3C4510B system. In the S3C4510B system, the entry address of the exception interrupt vector table is fixed whether before or after address remapping (see Table 1). When the system runs to the point where the exception interrupt condition is met and an exception interrupt occurs, the system will automatically jump into the corresponding exception interrupt vector table. What is saved in the exception vector table is the instruction program that uses the jump instruction or ldr instruction to point to the exception interrupt handler of the interrupt, thus realizing the installation of the exception interrupt handler. Taking the SWI soft interrupt as an example, the basic sequence of the exception interrupt installation is shown in Figure 2, where the address of the exception interrupt vector is fixed and the other addresses are assumed.

2.1 Using the jump instruction to realize the installation of the exception interrupt

Placing the BL instruction at a specific position in the interrupt vector table and the jump target address is the first address of the interrupt handler can directly realize the installation of the exception interrupt. The advantage is that the BL instruction can directly save the address, and the disadvantage is that the jump range of BL is only 32MB of address space, such as bl SWI_Handler.

2.2 Using the ldr instruction to implement the installation of the exception interrupt

The interrupt handler can also be installed by using ldr to directly assign values ​​to the program counter PC. First, the absolute address of the first address of the exception interrupt handler must be placed in an adjacent storage unit, and then the address in the memory unit is read into the PC using the ldr command. The advantage is that the range of callable programs is not limited, such as:

ldr pc,SWI_ADDR
…
SWI_ADDR dcd SWI_Handler
The above two installation methods have their own advantages and disadvantages, and need to be selected according to actual conditions. Electronic Technology Book Network

3 SWI exception interrupt example in S3C4510B system

The SWI instruction in S3C4510B can be used to implement system function calls in RTOS. It is triggered by the currently executed instruction in user mode, and a 24-bit immediate value is used to refer to the system function that SWI needs to call. The call execution process is performed in privileged mode.

3.1 SWI abnormal interrupt handler

Usually we divide the SWI interrupt handler into two levels, which respectively complete the reading of immediate data and the execution of function call. The instruction code is as follows:
...

stmfd sp!,{r0-r12,lr}
protects the context and saves the register value
ldr r0,[lr,#-4]
lr register save instruction
bic r0,r0,#0XFF000000 ; read the 24-bit immediate number in the instruction
...
cmp R0,#MaxOfSWI
to determine whether the immediate number is valid
ldrls pc,[pc,r0,lsl #2]
b OutOfSWIRange ; out of range
JumpListofSWI
dcd SWIPro_0
dcd SWIPro_1
...
all other soft interrupt entries
SWIPro_0
enters the interrupt handler corresponding to the immediate number 0 of SWI
...
the interrupt handler corresponding to the immediate number 0
b EndOfSWI
SWIPro0
enters the interrupt handler corresponding to the immediate number 1 of SWI
...
the interrupt handler corresponding to the immediate number 1
b EndOfSWI
...
other SWI handlers
EndOfSWI
1dmfd sp!,{r0-r12,pc}^
Restore each register[page]

3.2 Call and return of SWI abnormal interrupt

The call of SWI abnormal interrupt should be made according to the processor mode where the interrupt site is located. Usually, calling the SWI function in user mode only requires storing the parameters required by the processor in the register, and then calling the system function of the corresponding function number.

Mov r0, #80
Assume that the parameter is #80
swi 0X1
SWI interrupt immediate value 1
Since the SWI interrupt function call is executed in privileged mode, when calling the SWI function in privileged mode, the SPSR and register LR in the current mode must be saved.
stmfd sp!,{r0－r12,lr}
save register
mov r1,sp
mov r0, spsr_svc
stmfd sp!,{r0} ; save SPSR
……
read immediate data, call SWI interrupt handler
ldmfd sp!,{r0} ; restore SPSR
msr spsr_svc, r0
ldmdf sp!,{r0-r12,lr}^ ; restore other registers

4 IRQ abnormal interrupt example in S3C4510B system

4.1 Generation of IRQ abnormal interrupt

S3C4510B processor system is often used to respond to external abnormalities and control operating system processes. When the I control position of the CPSR register is 0, the processor queries whether there is an IRQ request at the instruction boundary, and the system's external interrupt manager or peripheral generates an IRQ abnormal interrupt by enabling the processor's IRQ input pin.

4.2 IRQ abnormal interrupt handler

After the IRQ abnormal interrupt is generated, the corresponding interrupt handler is jumped according to the instruction of the interrupt vector. The system's peripheral interrupt management hardware will arrange the IRQ interrupt requests used according to priority and put the information of the highest priority IRQ interrupt into the register. The usual IRQ interrupt handler also needs to save the return address and register, and needs to mask the IRQ interrupt to ensure that the higher priority interrupt is fully processed.
sub lr,lr,#4
stmfd sp!,{lr}
Save the return address
mrs r14,spsr_irq
stmfd sp!,[r12,r14]
Save r12,spsr
mov r12,#IntBase
Read the base address of the interrupt management interface

ldr r12,[r12,#IntLevel]
Calculate the physical address of the current interrupt
mrs r14,cpsr
bic r14,r14,#0X80
Clear the IRQ interrupt disable bit
msr cpsr_irq,r14
Enable IRQ interrupt
ldr pc,[ pc,r12,lsr #2]
Jump to the corresponding interrupt handler
dcd PirQ0Handler
dcd PirQ1Handler
…
dcd PirQnHandler
The interrupt handler address of priority n
PirQ0Handler
stmfd sp!,{r0-r11}
…
Interrupt handler of priority 1
ldmfd sp!,{r0-r11}
msr spsr_irq,r14
restore r12 and spsr
ldmfd sp!,{pc}^; return in the middle
...
dcd PirQnHandler
interrupt handler with interrupt priority N
...

4.3 Application of IRQ abnormal interrupt in process control

The switching between processes in the S3C4510B processor system is also completed through IRQ. Each process in the operating system is represented by a process control block PCB, which contains process-related information. For example, when a process reaches a certain level, the IRQ interrupt is used to interrupt the current process, save the value of the register that needs to be saved, and then switch to another process for execution.

5 Conclusion

The abnormal interrupt mechanism of S3C4510B is relatively complex, but it is precisely because of its complex mechanism that we have more flexible choices in the development process. Using abnormal interrupts well can not only achieve real-time response of the system, but also greatly help improve system efficiency and overall performance. I hope this article can be helpful to the developers of S3C4510B system.

References

1 Du Chunlei. ARM Architecture and Programming. Beijing: Tsinghua University Press
2 Ma Zhongmei, Ma Guangyun, etc. ARM Embedded Processor Structure and Application Basics. Beijing: Beijing University of Aeronautics and Astronautics Press, 2002.6
3 S3c4510b Data Sheet. SAMSUNG.1999.3
4 ARM Limited. Developer suit (Version 1.1), Assembler Guide.ARM DUI 0068A,2000