The control method of interrupt priority of MCS-96 series single chip microcomputer

1. Introduction
In many literatures [1,2,3], although it is pointed out that the interrupt priority of the MCS-96 series microcontroller can be changed by software, no in-depth explanation is given. In fact, the interrupt system of this series of microcontrollers is quite unique, and the control of interrupt priority is very flexible. Users can use a combination of software and hardware to arrange the priority of various interrupt sources at will.

2. MCS-96 Series MCU Interrupt
Characteristics of Priority Structure
The hardware priority queue circuit of the MCS-96 series MCU interrupt system specifies the priority order for various interrupt sources. This interrupt priority structure has the following characteristics.
(1) The hardware queue circuit cannot guarantee the priority of each interrupt source. This is because after the interrupt request of a certain interrupt source is responded to by the CPU, the corresponding bit in INT-PENDING is cleared, which means that the interrupt source being serviced cannot participate in the priority comparison after a new interrupt request. If certain measures are not taken, it will result in the interrupt service of a higher level being interrupted by an interrupt request of a lower level. For example, when an external interrupt (highest priority) and a timer overflow interrupt (lowest priority) are generated at the same time, if the system has enabled interrupts, the external interrupt request will be responded to by the CPU first. After entering its interrupt service program, the timer overflow interrupt request will be compared by the priority encoding circuit. Since the bit corresponding to the external interrupt in INT-PRNDING has been cleared, only the timer overflow interrupt is involved in the priority comparison. Therefore, the service process of the external interrupt is interrupted, and the CPU turns to the timer overflow interrupt service program. After the service is completed, it returns to continue serving the external interrupt. It is not difficult to see that when multiple interrupt sources make interrupt requests, the interrupt source with the lowest level will actually be the first to receive complete service, and the interrupt source with the highest level will have to wait until the end to be completed. This also means that the highest level interrupt source actually becomes the lowest level.
(2) A combination of software and hardware can be used to implement a specific priority order. Although as mentioned above, the hardware queuing circuit cannot guarantee interrupt nesting in the specified priority order, certain software measures can be taken to implement the priority queuing order expected by the designer.

3. Software measures to implement a predetermined priority queue order
To implement a specific interrupt priority order, corresponding measures need to be taken in software. The following four cases are discussed.
3.1 Implementing the priority order specified by hardware
The hardware circuit specifies the priority order of 8 interrupt sources, that is, the external interrupt has the highest priority, the serial port interrupt is the second, and the timer overflow interrupt has the lowest level. Implementing this priority specified by hardware has two meanings: one is that when multiple interrupt sources make interrupt requests, the CPU responds to the request with the highest priority first; the other is that a high-level request can interrupt a low-level service process, but not vice versa. The specific steps are as follows:
(1) First, set INT_MASK in the main program and execute the instruction LDB INT_MASK, #0FFH to make its content all 1 to open all interrupts, so that when any interrupt source or multiple interrupt sources make interrupt requests, the CPU responds to all of them.
(2) At the beginning of each interrupt service routine, execute the DI or PUSHF instruction to disable all interrupts, then clear all bits in INT-MASK that have a lower priority than this interrupt, and set all bits that have a higher priority than this interrupt to 1, and then execute the EI instruction to enable interrupts. After doing so, during the execution of the interrupt service routine, low-level interrupts cannot achieve interrupt nesting, while high-level interrupts can. At the end of the interrupt service routine, INT-MASK should be set to FFH again so that the CPU can respond to any interrupt again after the interrupt returns. This ensures the priority order specified by the hardware.
The following is an example of the instructions required at the beginning and end of the HSO interrupt service routine using the above method.
INT-SHO: PUSHF
LDB INT-MASK, #0F0H
EI
.
.
.
POPF
RET
The PUSHF instruction protects the contents of PSW and turns off the general interrupt switch; since the HSO event interrupt corresponds to the D3 bit in INT-MASK, the LDB INT-MASK, #0F0H instruction only allows interrupts higher than the HSO event; the POPF instruction restores PSW, which also makes INT-MASK = 0FFH, because FFH has been sent to this register in the main program. [page]
3.2 Do not allow any interrupt to interrupt
the interrupt service program that is running
. The method is relatively simple. After entering the interrupt service program, turn off the interrupt (make PSW.9 = 0), and turn on the interrupt until the end of the interrupt service program. The program example is as follows:
INTSUB: PUSHF (or DI)
.
.
.
POPF (or EI)
RET
PUSHF makes PSW.9 = 0, thereby disabling all interrupts. During the operation of the interrupt service program, the interrupt is not allowed to be opened until the program ends. This ensures that no interrupt request can interrupt the ongoing service process.
3.3 Make any interrupt source the highest level
This means that the user arranges the interrupt request of a specific interrupt source to interrupt any interrupt service program and realize interrupt nesting, ensuring that the specified interrupt source can get priority service under any circumstances. The specific method is to turn off the general interrupt at the beginning of each interrupt service program, and then set INT-MASK to only open the interrupt set to the highest level.
Assuming that the specified A/D conversion end interrupt can interrupt any service process, the interrupt service program of the external interrupt is designed as follows:
EXTINT: PUSHF; turn off the general interrupt
LDB INT_MASK, # 02H; only allow the A/D conversion end interrupt
EI; open the interrupt
.
.
.
POPF
RET
3.4 Arrange the priority level of each interrupt source
According to the actual needs of the system, the priority of each interrupt source can be rearranged to make it different from the interrupt priority specified by the hardware. The specific method is to turn off interrupts at the beginning of each interrupt service program, and then set INT-MASK to only enable predetermined high-level interrupts. Assuming that the order of priority from high to low is: timer overflow interrupt, external interrupt, A/D conversion end interrupt, the corresponding three interrupt service routines can be designed as follows:
TIMERV: PUSHF; timer overflow interrupt service routine
.
.
.
POPF
RET
EXTINT: PUSHF; external interrupt interrupt service routine
LDB INT_MASK, # 01H; only open timer overflow interrupt
EI
.
.
.
POPF
RET
AD-INT: PUSHF; A/D conversion end interrupt service routine
LDB INT_MASK, # 81H; open timer overflow interrupt and external interrupt
EI
.
.
.
POPF
RET
In the A/D conversion end interrupt service routine, the timer overflow interrupt and external interrupt are opened, then these two types of interrupts can interrupt the running of the program; in the external interrupt interrupt service routine, only the timer overflow interrupt is opened; and in the running of the timer overflow interrupt service routine, any interrupt is prohibited, thus ensuring the realization of the predetermined interrupt nesting.

4. MCS-96 Series MCU Interrupts
Summary of Priority Control
As mentioned above, the MCS-96 series MCU has a unique interrupt structure, and the control of interrupt priority is extremely flexible. Although the hardware queuing circuit specifies priorities for various interrupt sources, the interrupt source being served does not participate in the priority comparison when there is a new interrupt application, which results in the high-level service process being interrupted by the low-level application. However, as discussed above, certain software measures can be taken to implement the predetermined priority queuing scheme, that is, according to different situations, the interrupt service program can be turned off and on and the interrupt mask register INT-MASK can be set to achieve the purpose. Obviously, this method allows users to arrange the priority order of interrupt sources at will, which has great flexibility and brings convenience to the design of the interrupt system and software programming.

5. References
[1] Jin Panshi, Wang Yongming. Detailed explanation of the application of INTEL96 series single-chip microcomputers. Beijing: Electronic Industry Press, 1992
[2] Zhang Zhenan, Zhang Peiren. Principles and practice of MCS-96 series single-chip microcomputers. Hefei: University of Science and Technology of China Press, 1993
[3] Zhu Xiaoqiang, Yao Zhishi. Principles and applications of 8096/8098 single-chip microcomputers. Shanghai: Fudan University Press, 1993