Design of interface between MCS-51 single chip microcomputer and PLD programmable device

1 Introduction

In the field of electronic design technology, the widespread use of programmable logic devices has brought great flexibility to the design of digital systems. Since the device can reconfigure the structure and working mode of its hardware through software programming, the design of hardware can be as convenient and fast as software design. This has greatly changed the traditional digital system design method and design process.

As we all know, the single-chip microcomputer has the characteristics of high performance-price ratio, flexible functions, easy human-computer dialogue, and good data processing capabilities. PLD has the advantages of high integration, high speed, high reliability, and convenient and standardized development. As far as the currently commonly used intelligent instruments and industrial measurement and control systems are concerned, the application field of the integrated electronic system composed of PLD and single-chip microcomputer as core components is very broad. If the flexible control function and good human-computer dialogue function of the single-chip microcomputer are combined with the high speed and high reliability of the PLD, it will effectively break through the obstacles in the design of traditional electronic systems and greatly improve the performance of electronic systems. This article will discuss the interface problem between MCS-51 and PLD.

2 Interface Mode

There are generally two ways to interface a single-chip microcomputer with a PLD device: independent mode and bus mode. The timing of independent communication can be freely determined by the designed software, and the form is flexible and diverse. Its biggest advantage is that the interface logic does not need to follow the fixed bus mode read and write timing in the single-chip microcomputer. The logic design of the PLD and the single-chip microcomputer program design of the interface can be completed relatively independently in sequence. Therefore, the independent mode is relatively simple and will not be introduced in detail here.

The single-chip microcomputer communicates data with the PLD device in bus mode. For the single-chip microcomputer, its programming is simple and reliable compared to the non-bus mode. Only one single-byte instruction is needed to complete the required read and write operations, such as MOV @DPTR, A; MOV A, @DPTR. Its communication is a pure hardware behavior, so it is fast. For PLD devices, I/O port lines can be saved, as shown in Figure 1. Through 19 I/O port lines, various data information can be exchanged between the single-chip microcomputer and the PLD device.


To design the interface logic for the single-chip microcomputer and the PLD device to communicate in bus mode, it is necessary to understand the bus read and write timing of the single-chip microcomputer in detail. Figure 2 is the timing diagram of the MCS-51 single-chip microcomputer. ALE is the address latch enable signal. Its falling edge can be used to latch the lower 8-bit address into the address latch of the PLD through the P0 port. At the same time, the upper 8-bit address is at the P2 port. The microcontroller uses the low level of the read instruction enable signal PSEN to read the instruction from the P0 port. The timing of reading the instruction is before the rising edge of PSEN arrives. Then, the upper 8-bit and lower 8-bit data addresses are output from the P2 port and the P0 port respectively, and the lower 8-bit address of the P0 port is latched into the address latch by the falling edge of ALE. The microcontroller can make RD a low level through the instruction MOV A, @DPTR, and read the data latched in IN1 (or IN2) into accumulator A through the P0 port. If you want to send the data of accumulator A to the PLD, you can generate the write enable signal WR through the instruction MOV @DPTR, A, so that the decoder outputs the WR-ENABLE signal, thereby writing the data into the output latch.

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3 Interface Programming

In recent years, with the continuous development of EDA technology, people generally accept VHDL language among various description languages. This language has the reputation of "World Language" in the field of electronic design. The interface software of this design is written in VHDL language. Due to space limitations, only the VHDL program of the construct is given here: ． ． ． ． ． ．
．
BEGIN
PROCESS(ALE)
BEGIN
IF ALE'EVENT AND ALE='0'THEN
LATCH-ADDERS<=P0; END IF;END PROCESS; =
' 1';END IF;END PROCESS; PROCESS(WR-ENABLE)
BEGIN
IF
WR -ENABLE'EVENT AND WR-ENABLE='1' THEN OUT1<=P0;END IF;END PROCESS; PROCESS(P2, LATCH -ADDRES,READ,RD) BEGIN IF(LATCH-ADDRES="01101110")AND(P2="11110001")AND(READY='1')AND(RD='0') THEN P0<=IN1; ELSE P0<="ZZZZZZZZ";END IF;END PROCESS; PROCESS(DIN1) BEGIN IF DIN1'EVENT AND DIN1='1' THEN IN1<=DIN1;END IF;END PROCESS; PROCESS(P2,LATCH-ADDRES,READ,RD) BEGIN IF(LATCH-ADDRES="01101010")AND(P2="11110011")AND(READY='1')AND(RD='0') THEN P0<=IN2; ELSE P0<="ZZZZZZZZ";END IF;END PROCESS; PROCESS(DIN2) BEGIN IF DIN2'EVENT AND DIN2='1' THEN IN2<=DIN2;END IF;END PROCESS; DOUT1<=OUT1; ． ． ． ． ． ． For example, the instruction for AT89C51 to send data 4DH to OUT1 is: MOV A, #4DH MOV DPTR, #F5F0H MOVX @DPTR, A When READY is high, the instruction for AT89C51 to read data from IN1 of PLD device is: MOV DPTR, #F16EH MOVX A, @DPTR The instruction for AT89C51 to read data from IN2 of PLD device is similar to that to read data from IN1 of PLD device, the only difference is the entry address.

4 Conclusion

This article uses the Lattice company's PLD device ISPLSI1032 and the interface circuit designed based on the VHDL description language. It has the advantages of small size, reliable performance, convenient development, and few peripheral components. The circuit design adopts a top-down system design method. Using the software and hardware circuits introduced in this article, combined with specific design occasions, various forms of interface circuits can be transformed.