ARM off-chip FIash memory IAP solution

introduction

Embedded application systems with ARM chips as processor cores have gained more and more popularity due to their small size, low power consumption, low cost, high performance, rich on-chip resources and wide support for operating systems. In-Application Programming (IAP) is such a self-modifying program. It first writes data values ​​in the RAM memory, then points the PC to the storage segment and executes the segment as a program segment. Many ARM7 chips have built-in IAP processors, which can be used to conveniently program the Flash memory integrated in the chip. However, almost all ARM core chips do not support off-chip IAP processing, because the off-chip Flash memory is selected by the user, and the chip manufacturer cannot foresee it. In addition, the programming timing of different Flash memories is also different, which makes it impossible for chip manufacturers to provide universal IAP codes. So, how to program the off-chip Flash memory of the embedded system in-application? There are two situations: one is that the normal code is stored in a separate off-chip Flash, and the IAP code is completed in another Flash. At this time, just execute the IAP code according to the operation sequence of the Flash to complete the erase or write operation. Although this situation is simple, two Flashes are used; and the IAP code is very small and can generally be integrated into one chip, so this situation is not considered here. Another situation is that one Flash needs to store both normal code and IAP.

Aiming at the problem that there is no ready-made solution for IAP of off-chip Flash memory in embedded application system, this paper introduces an IAP solution of off-chip memory based on the idea of ​​code reentry. Combining LPC2210 and SST39VFl60 chips, this paper briefly introduces the characteristics of the two chips, gives the application connection block diagram; analyzes the key points of IAP implementation, and gives the implementation code of IAP. Taking LPC2210 of Phnips Company and SST39VFl60 of Silicon storage Technology Company as examples, this paper discusses the IAP solution in detail.

1 Hardware Structure

1.1 Introduction to LPC2210

Philips' LPC2210 is a microcontroller based on the 16/32-bit ARM7TDMI-SCPU that supports real-time simulation and embedded tracing. The chip uses a 144-pin package, has 16 KB on-chip static RAM, and an open external bus; the external memory can be configured into 4 groups through the external memory interface, with a capacity of up to 16 Mb per group and data width of 8/16/32 bits; it has multiple 32-bit timers, 8-way 10-bit PWM outputs, multiple serial interfaces (including 2 16C550 industrial standard UARTs, high-speed I2C interfaces and 2 SPI interfaces) and 9 external interrupts, up to 76 general-purpose I/O ports that can withstand 5 V voltage, and an embedded real-time clock and watchdog. The on-chip peripherals are rich and powerful; the on-chip crystal oscillator frequency range is 1 to 30 MHz, and the on-chip PLL can achieve a maximum CPU operating frequency of 60 MHz. It has two low-power modes - idle and power-down. The processor is woken up from the power-down mode through external interrupts, and power consumption can be optimized by enabling/disabling external functions individually. The above features make it particularly suitable for industrial control, medical systems, access control and POS machines. It is also very suitable for communication gateway protocol converters, embedded soft modems, and various other types of applications.

1.2 SST39VFl60 Introduction

The SST39VFl60 from Silicon Storage Technology is a 1M x 16b CMOS multi-function Flash device with single voltage read and write operations over a voltage range of 3.0 to 3.6 V. It is available in 48-pin TSOP and 48-pin TFBGA packages.

The main operations of this device include read, word programming, sector/block erase and chip erase operations. Erasing and word programming must follow a certain timing. Table 1 lists the sector erase and word programming process and timing. Reading the trigger bit DQ6 during the erase or programming operation will result in a cyclic jump of "1" and "0"; and reading DQ6 after the operation is completed will result in an unchanged fixed value. This is the write operation status detection software method provided by the device.

1.3 Hardware Connection

SST39VF160 is used as the system program memory, and LPC2210's CSO is used as the chip select signal of Flash. After the processor configures the Boot pin to a 16-bit data bus width, the code in SST39VF160 can be directly executed after power-on. This Flash chip has a 16-bit data width and no byte control bus, so the BLS pin of LPC2210 is not used in the application. The system structure diagram is shown in Figure 1.

2 Software Implementation

2.1 Analysis of Key Points of IAP Implementation

In embedded application systems, it is usually required to record some on-site sensing and interactive input data, and the data is usually recorded in the Flash memory so that the previous data can be obtained next time the power is turned on. If the system program and data are stored separately, then it is sufficient to program the Flash device that stores the data. However, in most embedded systems, the program and the data to be saved coexist in the same Flash memory. So, can the Flash memory be directly programmed as mentioned above? Both theory and practice show that it is not possible. First, calculate theoretically: the chip core operating frequency (CCLK) range allowed by LPC22lO is 10 to 60 MHz, and the memory read access length is controlled by the read access length field control WSTl in the memory group configuration register BCFG. The maximum available length is 35 CCLKs, and the typical sector erase time of SST39VFl60 is 18 ms. The following is the calculation formula:

TRDmax=RDLenmax/CCLKmin=35/10×10-6=3.5 μs

.TD=18 ms》3.5μs

Where: TRDmax—maximum read access time;

RDLenmix – Maximum length available for read access;

CCLKmin——minimum core operating clock frequency;

Tp——Typical time for sector erase.

The formula shows that the typical time of sector erasing is much longer than the maximum read access time. In this way, if data is written to a Flash and pre-fetched at the same time, the data pre-fetched must be uncertain data on its data pin because the Flash does not respond to other operations during the execution of the command, and the pre-fetch fails. Practice also shows that if the same Flash is sector-erased during program execution, it will definitely cause a pre-fetch interrupt.

In order to solve the problem of storing programs and IAP in the same Flash chip, the idea of ​​code remapping is introduced. The so-called remapping is that the code is first copied to the specified storage area, and then jumps to the starting point of the specified area to start execution. Here, the lAP program is first copied to the SRAM on the LPC2210 chip, and then jumps to the SRAM to execute the lAP code. As mentioned earlier, ARM7 is a von Neumann structure, which makes it possible to remap the IAP program.

The key to writing remappable code is to solve the problem of relative offset in the program. The instructions involving relative offset in the ARM7 instruction series mainly include LDR/STR and jump instructions. The solution here is: all instructions involving offset values ​​use base address displacement addressing mode, with the PC register as the base register and the immediate value as the displacement. In this way, when the entire program block is moved, the offset value between the data to be loaded or the address to be jumped and the current PC value is fixed, solving the relative offset problem.

2.2 Sector Erase

The program pre-programmed in Flash is first copied to the location specified by SRAM, and then PC is assigned as the starting point ERASEPART of the sector programming code segment in SRAM. The program starts to execute at the starting point of ERASEPART in SRAM, and starts erasing according to the timing requirements of SST39VF160 sector erasure. According to the ATPCS regulations proposed by ARM, when a C language program calls an assembly program, registers R0 to R3 pass parameters, and the return value is passed by register RO. A parameter of the sector erase program, the sector number to be erased, is passed by RO; the return parameter is placed in R0, and "1" is returned if the sector is successfully erased, otherwise "0" is returned.

2.3 Word Programming

The program starts to execute at the PROGRAMPART starting point in SRAM and starts programming according to the timing requirements of SST39VFl60 word programming. There are three entry parameters, namely programming address, data starting address, and programming data length. If word programming is successful, it returns "1", otherwise it returns "0".

3 Conclusion

The method proposed in this paper to re-enter the IAP code into the SR-kM for execution effectively solves the IAP problem of embedded systems using 32-bit ARM processors without on-chip program memory, and has great application value.