Design of Automatic Phase-locked FM Transmitter Controlled by Single Chip Microcomputer

0Introduction ​

Since the birth of radio technology, information transmission and information processing have always been its main tasks. To effectively transmit radio signals, the size of the antenna must be of the same order of magnitude as the wavelength of the electrical signal ^[1] . In order to effectively transmit, the low-frequency electrical signal carrying information must be modulated into a high-frequency oscillation signal of tens to hundreds of MHz and then sent out through the antenna. In order to reduce the instability of the system caused by various factors and enhance the reliability of the system, the system must include feedback control circuits including automatic gain control, automatic frequency control and automatic phase control (phase-locked loop). Among them, the performance of the phase-locked loop circuit is particularly important. This article discusses the design of a direct frequency modulation signal synthesizer and a low-power transmitter composed of a phase-locked loop, thereby forming an FM transmitter station.

1 Overall design of the system

1.1 Basic principles of FM transmitters

The principle of the transmitting station is very simple, as shown in Figure 1. The low-frequency electrical signal carrying information is modulated into a high-frequency signal, which is then amplified by a high-frequency power amplifier and transmitted by the antenna.

Figure 1 Basic block diagram of the transmitting station

Figure 2 System overall implementation block diagram

1.2 Overall implementation block diagram ^[2]

This design adopts the scheme of direct frequency modulation by phase-locked loop, which not only has high frequency stability (about 10-6), but also has a relatively high maximum frequency deviation. The overall system block diagram is shown in Figure 2. The crystal oscillator provides the reference frequency signal for the oscillation source, and the oscillation source adopts the PLL frequency synthesis method. Frequency modulation is achieved by adding the modulation signal directly to the voltage-controlled oscillator. The voltage-controlled oscillator is a capacitor three-point oscillator composed of a varactor diode and a crystal triode. The RF power amplifier adopts a relatively efficient Class C power amplifier. The entire system is controlled and displayed by a single-chip microcomputer.

2. Principles of each main part

2.1 Working principle of phase-locked loop ^[3][4]

The most basic structure of a phase-locked loop is shown in Figure 3. It consists of three basic components: a phase detector (PD), a loop filter (LPF), and a voltage-controlled oscillator (VCO). The phase detector is a phase comparison device that compares the phase of the input signal Si(t) and the output signal So(t) of the voltage-controlled oscillator to generate an error voltage Se(t) corresponding to the phase difference between the two signals. The function of the loop filter is to filter out the high-frequency components and noise in the error voltage Se(t) to ensure the required performance of the loop and increase the stability of the system. The voltage-controlled oscillator is controlled by the control voltage Sd(t), so that the frequency of the voltage-controlled oscillator approaches the frequency of the input signal until the frequency difference is eliminated and locked.

Figure 3 Basic structure of a phase-locked loop

Figure 4 Block diagram of a pulse-swallowing digital phase-locked frequency synthesizer

The phase-locked loop is essentially a phase error control system. By comparing the phase difference between the input signal and the output signal of the voltage-controlled oscillator, an error control voltage is generated to adjust the frequency of the voltage-controlled oscillator to achieve the same frequency as the input signal. When the loop starts working, if the input signal frequency is different from the voltage-controlled oscillator frequency, the phase difference is bound to change all the time due to the inherent frequency difference between the two signals, and the error voltage output by the phase detector changes within a certain range. Under the control of this error voltage, the frequency of the voltage-controlled oscillator is also changing. If the frequency of the voltage-controlled oscillator can be changed to be equal to the frequency of the input signal, it will stabilize at this frequency under the condition of stability. After reaching stability, the frequency difference between the input signal and the output signal of the voltage-controlled oscillator is zero, the phase difference no longer changes with time, the error voltage is a fixed value, and the loop enters the "locked" state.

2.2 The structure of the pulse-swallowing digital phase-locked frequency synthesizer

In order to ensure a sufficiently small channel spacing and a relatively high operating frequency, a pulse-swallowing digital phase-locked frequency synthesizer can be used. The so-called "pulse-swallowing" technology is to use a high-speed dual-mode pre-divider to control its division ratio to P or P+1 according to the level of the mode control. The structure of this type of digital phase-locked frequency synthesizer is shown in Figure 4.

In the figure, fr is the reference frequency, fP is the feedback frequency, NP and A are the division ratio coefficients, and fvco is the output frequency of the voltage-controlled oscillator. The variable-mode pre-division phase-locked loop frequency synthesizer uses an absorption counter, a main counter, and a dual-mode pre-divider to form a "swallow pulse" division technology to divide the voltage-controlled oscillation frequency. After the absorption counter has preset the division ratios NP and A, it is in a subtraction counting working state during the counting period. The dual-mode pre-divider has two division ratios P ​​and (P+1). The switching of the division ratio is controlled by the mode control signal generated by the absorption counter. During the counting period of the absorption counter, the mode control signal is high and the division ratio of the pre-divider is (P+1). Only when the absorption counter subtracts and counts to zero and stops counting, it outputs a low-level mode control signal to control the division ratio of the pre-divider to become P. The working process is as follows:

First, the frequency division ratio NP and A are preset to the main counter and the absorption counter through the preset circuit. The high-level mode control signal generated by the absorption counter makes the pre-divider work in the (P+1) state. When a counting cycle starts, before the main counter and the absorption counter have counted to zero, the mode control is high, and the output frequency of the dual-mode pre-divider is fvco/(P+1). After inputting A (P+1) cycles, the absorption counter counts down to zero, changes the mode control level to a low level, and blocks the counting prohibition end of the absorption counter through the AND gate circuit to stop counting. At this time, the main counter still has fvco/P. After (NP-A)P cycles, the main counter also counts down to zero, and the main counter outputs a low level to send two output phase comparison pulses to the phase detector. In a complete cycle, the number of input cycles is:

N = (P+1)×A+(NP-A)×P = P×NP+A

Where N is the total frequency division ratio. From the above formula, we know that NP must be greater than A. Once the loop is locked, the voltage controlled oscillator outputs (P × NP + A) times the reference frequency signal.

3. Main hardware circuit implementation

This design involves the design of high-frequency small signal buffer amplifier, voltage-controlled oscillator, phase-locked loop circuit, high-frequency power amplifier and single-chip microcomputer control part. The following mainly introduces the design of phase-locked loop circuit and single-chip microcomputer control part.

Figure 5 Voltage controlled oscillator

Figure 6 Modulation signal input circuit

3.1 Phase-locked loop design

The phase-locked loop is composed of an integrated phase-locked controller, a loop filter and a voltage-controlled oscillator. These parts are described in detail below.

3.2.1 Design of voltage - controlled oscillator

The VCO circuit is shown in Figure 5. The frequency range of the designed FM carrier frequency of this system is 85MHz~110MHz, the center frequency f0=(85+110)/2=97.5MHz, for the convenience of calculation, f0=98MHz, the band coverage factor is Kf=110/85=1.3, the capacitance ratio of the varactor is , the requirement , the general capacitor three-point oscillator can achieve. The varactor diode D1 adopts a partial access type.

3.2.2 Design of FM circuit

The modulation signal is directly added to the oscillation circuit of the phase-locked loop voltage-controlled oscillator to achieve direct frequency modulation, which can take into account both the maximum frequency deviation and frequency stability. Considering that the peak-to-peak value of the input modulation signal is uncertain, such as the modulation signal can reach 1V when the output is a CD player, but only 0.5V when the input is a cassette tape player, a potentiometer is added to the modulation signal input end for adjustment to achieve the required frequency deviation. In addition, a low-pass filter is also set in the input circuit to filter out high-frequency interference and increase the signal-to-noise ratio of the output FM signal. R2, RP2 and R3 provide a DC bias voltage for the varactor D1 to reduce the modulation distortion caused by the nonlinearity of D1. The circuit is shown in Figure 6:

3.2.3 Design of Integrated Digital Phase-Locked Loop

This design uses the large-scale integrated digital phase-locked frequency synthesizer MB1504 from Fujitsu of Japan. MB1504 uses Bi-CMOS technology and is a single-chip serial integrated phase-locked frequency synthesizer chip with pulse swallowing function. The B1504 series includes the main components such as internal oscillator, reference divider, programmable divider, phase detector, latch, shift register, dual-mode high-speed pre-divider and one-bit control latch. A complete frequency synthesizer can be formed by external loop filter, voltage-controlled oscillator, single-chip microprocessor and other circuits.

The design uses a high-precision reference crystal frequency of 8MHz, and the reference frequency is set to Rf = 2K, then the reference division ratio Np = 8M/2k = 4000. The pre-divider uses the 64/65 technology mode, and the frequency range is 85MHz-110MHz, then M = f/fR, N = [M/64], A = M-64·N, and the calculated range of M is 42500 to 55000, N is 664 to 859, and A is 4 to 63, which meets the preset number range of A = 0~127 and N = 16~2047 in MB1504. Within the above range, changing the preset values ​​of N and A can obtain an output sinusoidal signal with a frequency of f. The phase-locked loop circuit is shown in Figure 7.

The charge pump power supply voltage VP in MB1504 is 9V, which can obtain a larger controllable frequency range. The charge pump output DO outputs a smooth voltage after passing through a low-pass filter (LPF), which controls the voltage-controlled oscillator to output the required frequency. The signal output by the voltage-controlled oscillator is fed back to the inside of MB1504 through Fin to complete the loop capture, tracking and locking of the entire phase-locked loop. The preset data output by the microcontroller is serially input to MB1504 by CLK, Data and LE.

3.2.4 Single chip microcomputer control circuit and program design

Since the control function required by this design is relatively simple, it can be realized by using the AT89C2051 with relatively simple functions. The hardware system of the single-chip microcomputer is shown in Figure 8.

Figure 7 Phase-locked loop circuit

4. Software Design

The main tasks of the software are: to realize keyboard management, display and other human-machine interfaces; to control the phase-locked loop to realize the frequency increase and decrease. The main program flow chart is shown in Figure 9: The main program uses the query method to detect whether a key is pressed, if so, it will de-jitter, judge the key and perform corresponding operations such as changing the mode, increasing or decreasing the frequency, etc.

5. System Testing

The designed system was tested and the test results are as follows:

1) Frequency range: The oscillating output waveform is displayed on an oscilloscope and there is no obvious distortion. The frequency range is 85MHz to 110MHz as measured by a digital frequency meter. Since a crystal oscillator is used in the phase-locked frequency synthesizer, the stability of the output signal frequency is better than 10 ^-6 .

2) Indicators of the resonant power amplifier: Use an oscilloscope to measure the peak-to-peak value Vp-p on the output load RL (50Ω) and get the output power:

Use the multimeter's DC current range to measure the power amplifier's current Ico, and get the amplifier's DC power consumption PD=Vcc · Ico . The efficiency ηc＝Po/PD can be obtained. The measured data is shown in Table 1:

Table 1 Specifications of resonant power amplifier

6 Conclusion

This system uses a phase-locked loop dedicated chip in its design, which is stable and reliable, and can reach the level of practical use in terms of functions and indicators. The innovation of this paper lies in the use of single-chip microcomputer control technology, which realizes intelligent control, simplifies the structure of the system, improves the stability of the system, and enhances the overall function of the system.

References

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[2] Xie Zimei. Electronic Circuit Design, Experiment and Test (Second Edition) [M]. Wuhan: Huazhong University of Science and Technology Press. 2000.07:125-127

[3] Xie Jiakui. Electronic Circuits (Nonlinear Part, Fourth Edition) [M]. Beijing: Higher Education Press. 2000.05: 224-226

[4] Wang Fuchang. Phase-locked Principle[M]. Wuhan: Huazhong University of Science and Technology Press: 2004.08:136-138