Design of 4-frequency fast frequency hopping based on 51 single chip microcomputer and AD9858

In electronic systems, it is often necessary to apply frequency synthesis technology to realize frequency hopping source design. Frequency synthesis refers to various technical processing of a highly stable reference frequency to generate a series of stable frequency outputs. Currently, the most widely used is the phase-locked loop (PLL) frequency synthesis technology, which realizes frequency hopping by changing the frequency division ratio N in the PLL. However, the PLL cannot avoid the contradiction between the shortening of the loop locking time and the improvement of frequency resolution and the reduction of spurious signals. Therefore, it is difficult to meet the requirements of high-speed frequency hopping and fine step length and low spurious signals at the same time. Direct digital frequency synthesis (DDS) is a new frequency synthesis technology. It has the advantages of high frequency resolution, fast frequency switching, and phase continuity during frequency switching. Therefore, it is widely used in radar frequency hopping, communication, electronic countermeasures and other systems.

1 Basic principles of DDS

The principle block diagram of DDS is shown in Figure 1. Under the control of the A-bit frequency control word FCW, the phase accumulator uses the reference clock frequency fc as the sampling rate to generate a digital linear sequence of the phase of the signal to be synthesized, and then uses its high P bits as the address code to generate an S-bit digital sequence S(n) corresponding to the signal waveform by querying the sine table ROM, which is then converted into a step analog voltage waveform by the digital-to-analog converter and finally smoothed into a sine wave output by the low-pass filter LPF.

The frequency control word FCW and the clock frequency fc jointly determine the output signal frequency fo of the DDS. The relationship is:

Output frequency: f0 = FCW fc / 2A

The frequency resolution is: fo = fc / 2A 2 AD9858 features and data transmission method

Main features of AD9858:

● Has a sampling rate of 1 Gb/s;

● With input clock up to 2 GHz (by dividing by 2);

● Integrated 10-bit D/A converter;

● Contains 32-bit programmable frequency register;

● With 8-bit parallel and SPI serial control interface;

● With automatic frequency scanning function;

● Built-in 4 frequency registers;

● Powered by 3.3V low power supply;

● The independent power supply voltage of the charge pump can reach 5V;

● Integrated 2 GHz mixer.

Since the frequency generated by the DDS is controlled by the frequency control word FCW, the desired frequency can be obtained by changing the corresponding frequency control word. Therefore, the DDS data transmission method is one of the keys to realize the DDS frequency hopping source. Its internal structure block diagram is shown in Figure 2.

The AD9858 has two data transmission modes: parallel and serial. Data transmission from the user to the DDS device core requires two steps. During a write operation, whether using the parallel or serial data transmission mode, the user must first write the data into the I/O buffer. Only when the data is locked from the I/O buffer into the storage register, the DDS core receives the data. In the AD9858, triggering the FUD pin or changing the pre-programmed PROFILE can make the data in the I/O buffer enter the DDS core storage register.

(1) In parallel data transmission mode, the system should activate eight bidirectional data ports (D0~D7), six address input ports (ADDR5~ADDR0), one read port (RD) and one write port (WR). The register selection is determined by the address provided by the register diagram. The read and write functions are controlled by the RD and WR pulse triggers, but these two functions cannot work at the same time. The read and write data can be transmitted through the D0~D7 pins. (2) Serial data transmission mode includes two stages. The first stage consists of an 8-bit instruction cycle. The highest bit is the flag bit, which is used to determine whether it is a read operation or a write operation. The lower six bits are the address of the serial data transmission target register. The second stage is to send data to the register.

Many times, DDS requires fast frequency hopping, and the fast change of frequency requires the frequency control word of the register to be updated quickly. Therefore, DDS is usually required to use parallel data transmission. Compared with ADI's previous DDS chips, the advantage of AD9858 is that it has four frequency registers and four phase compensation registers, which makes it easy to quickly generate frequency hopping signals and four-phase code modulation signals, and its conversion time is extremely short. This is because the frequency control word of the frequency hopping has been sent to the four groups of control registers in the DDS core register, and the selection between frequency points is realized by external selection signals PS1 and PS0.

3 Fast frequency hopping design based on AD9858

3.1 Frequency Hopping Circuit

The number of transmission and the switching of four frequency points are completed by the single chip microcomputer. The 89C51 single chip microcomputer can work at a voltage of 5V, but experiments have shown that the 89C51 single chip microcomputer can work normally when the power supply is 3.3V. The frequency hopping principle diagram designed with single chip microcomputer and DDS chip AD9858 is shown in Figure 3.

3.2 Software Programming

According to the timing characteristics of AD9858, P1.0 and P1.1 of the microcontroller can be connected to RD and WR respectively. In this way, the address list of the frequency control word and phase compensation word can be set as follows during programming:

FTW0_1 EQU 00101011B

FTW0_2 EQU 00101111B

FTW0_3 EQU 00110011B

FTW0_4 EQU 00110111B

POW0_1 EQU 00111011B

POW0_2 EQU 00111111B

The lowest two bits are RD and WR, which are set high during initialization. Bits 3 to 6 are the address to send data. The program to send data for a frequency point is as follows:

MOV P3, 40H

MOV P1, #FTW0_1

ＣＬＲ ＷＲ＿

SET Ｂ WR ＿

SET FB FU Ｄ

CLR ＦＵＤ

MOV P3, 40H

MOV P1, #FTW0_2

ＣＬＲ ＷＲ＿

SET Ｂ WR ＿

SET FB FU Ｄ

CLR ＦＵＤ

MOV P3,40H

MOV P1, #FTW0_3

ＣＬＲ ＷＲ＿

SET Ｂ WR ＿

SET FB FU Ｄ

CLR ＦＵＤ

MOV P3, #40H

MOV P1, #FTW0_4

ＣＬＲ ＷＲ＿

SET Ｂ WR ＿

SET FB FU Ｄ

CLR ＦＵＤ

;

ＭＯＶ Ｐ３, #00Ｈ

MOV P1, #POW0_1

ＣＬＲ ＷＲ＿

SET Ｂ WR ＿

SET FB FU Ｄ

CLR ＦＵＤ

;

ＭＯＶ Ｐ３, #00Ｈ

MOV P1, #POW0_2

ＣＬＲ ＷＲ＿

SET Ｂ WR ＿

SET FB FU Ｄ

CLR ＦＵＤ

When designing, the 8-bit frequency control word should be sent to the P3 port of the microcontroller first, and then the 8-bit address should be sent to the P1 port. Since the 8-bit address is sent, WR is set to high. Therefore, by setting WR to low, the 8-bit control word and 6-bit address can be sent to the DDS buffer. Since the frequency update only requires a rising edge of FUD, setting FUD to high can send the 8-bit data to the specified frequency register (FUD has been set to low during initialization), and finally set FUD to low to prepare for the rising edge of the subsequent frequency update.

Through a simple procedure, the control word of one frequency point can be sent to the storage register of the DDS. Then, through the same address list and number sending method, the other three required frequency points can be sent to the storage register of the DDS. In this way, the four frequency points can be quickly switched through the external selection signals PS1 and PS0.

Since the frequency register inside the AD9858 is limited, when there are many frequency points for frequency hopping, the frequency control word needs to be changed each time the frequency hopping occurs. The actual frequency hopping time of the DDS includes the sending time and the internal switching time. If the internal register is used to control the switching frequency through PS1 and PS0, the frequency hopping time is only the internal switching time, so this type of frequency hopping is quite fast. 4 Experimental and test results

The experiment shows that (the experiment uses a 400MHz low phase noise clock): the internal switching time of the AD9858 is only nanoseconds. The experiment uses periodic logic levels to control PS1 and PS0, and realizes frequency switching by selecting PS1 and PS0 signals. Finally, a high-frequency oscilloscope is used to test the frequency hopping time.

The first experiment I conducted was to set the frequency point FCW of one register to 00000000H (0MHz) and the frequency point FCW of another register to 20000000H (125MHz). The test result was: the time taken to jump from 0MHz to 125MHz was 17.6ns.

The second experiment is to set the frequency FCW of one register to 19999999H (100MHz), and the frequency FCW of the other register to 20000000H (125MHz). The test result is: the time used to jump from 100MHz to 125MHz is 33.6ns.

5. Conclusion

From the results of the two tests, it is completely feasible to use the internal registers of the AD9858 to achieve fast frequency hopping. Due to the data transmission delay during the test, the rising edge of the PS0 and PS1 control levels, there is a certain error in the test, and the actual frequency hopping time should be shorter than the test result.

Since there are only four frequency registers inside the AD9858, the frequency hopping points are limited. This method is very advantageous when many frequency hopping points are not needed and the frequency hopping time is required to be very short.