Communication software design of 51 compatible carrier communication microcontroller PL3105

introduction

With the rapid development of embedded systems and integrated circuit technology, special chips designed for smart instrument applications have made great progress. Smart instruments generally have CPU units, display units, standard industrial bus interfaces, A/D signal conversion, real-time clocks, watchdogs and other functions. After selecting the CPU, traditional smart instrument equipment needs to be configured with complex functional chips and interface chips to complete display drive, external program storage, data storage and other required functions. The numerous interface chips lead to large size, high cost, increased power consumption, and reduced reliability of the instrument; at the same time, it is difficult to debug and maintain.

In order to meet the application needs of smart meters, the dedicated single-chip system-on-chip (SoC) solution for a certain type of product has gained great development opportunities. IC design companies at home and abroad have launched their own SoC products for different fields and different application needs. The SoC product PL3105 with 8051 instruction compatible high-speed microprocessor is manufactured using the latest CMOS digital/analog hybrid process. It is a low-cost, high-performance solution launched for the application of the smart meter industry. 1 Main features of PL3105

It uses a high-speed microprocessor compatible with 8051 instructions, making software easy to develop; it has an 8/16-bit dual-mode ALU, 8 times faster than the standard 51, fast running speed, and strong data processing capabilities. Figure 1 is a block diagram of the basic functional structure of PL3105.

For the application of intelligent instruments, PL3105 integrates 2-channel 16-bit precision ∑-Δ modulation A/D, LED (8×8 stroke type)/LCD (24×4 stroke type) display driver module, 2 UARTs, built-in 1KB RAM and 16KB E2PROM program memory (programmed in ISP mode); built-in low-power real-time clock. At the same time, it integrates complete voltage monitoring, power-on and power-off reset, and watchdog circuit to ensure the reliability of the system when running in an industrial environment.

The built-in carrier communication control unit enables the product to have the powerful functions of networking and remote communication on low-voltage power lines; the upgrade of the lowest voltage power line carrier communication interface dedicated chip PL2101 has the advantages of strong resistance to in-band co-frequency interference and high sensitivity. The embedded CPU controls the carrier communication by configuring registers, which is more convenient than the interface of the PL2101 chip and has higher reliability. 2 Working principle of carrier communication

Carrier communication uses direct sequence spread spectrum BPSK (Bipolar Phase Shift Keying) modulation and demodulation: the information to be sent is spread to a wider frequency band using a pseudo-random code sequence, and the same pseudo-random code sequence is used at the receiving end for synchronous reception and information recovery. The receiving process includes carrier signal capture and synchronization.

Capture is the process of the receiving module searching for the received signal before the spread spectrum sequence is accurately synchronized, so that the spread spectrum sequence of the received signal and the local spread spectrum sequence are within the range that can be synchronized in phase, that is, the phases of the two are within one spread spectrum sequence code element. The serial integral search method with a sliding step of half a bit is adopted. The maximum capture time theoretically requires 29 data bits (when the PN code is 15 bits). After the capture is completed, the tracking phase is entered, and the clock rate of the local pseudo code generator is dynamically increased so that the local pseudo code can automatically maintain accurate synchronization with the pseudo code of the received signal. The tracking circuit of the spread spectrum sequence adopts a fully digital baseband delay locked loop circuit.

To ensure that both capture and synchronization can be completed during the despreading process, the sending module sends at least 40 bits of all "1" before each transmission of valid data, which is used for capture and training as above (15-bit PN code).

Since the selected spread spectrum pseudo code has a strong autocorrelation, the correlation between the local pseudo code and the received sequence is compared with the set threshold to determine whether to stop the sliding of the pseudo code and complete the capture. When the rate is 500bps, the default capture threshold is 30H. The spread spectrum and despreading of the carrier communication are completely implemented by the hardware circuit inside the SoC, which is simple and reliable, and the despreading threshold can be adjusted by software.

Figure 2 (a) and (b) are the timing diagrams of the carrier communication sending/receiving operation inside the PL3105. The send and receive data bits are connected to P3.7 inside the chip, and the chip is not packaged and led out.

The carrier communication controller uses frame synchronization serial shift communication, half-duplex mode, 500bps/250bps optional rate; center frequency is 120kHz, bandwidth is ±7.5kHz. The embedded CPU uses external interrupt 2 (INT2) to synchronize the receiving and sending interrupts. The carrier communication configuration process is shown in Figure 3.

① Enable INT2 interrupt (EX2=1), and set it to falling edge trigger mode (IT2=0).

② Enable the carrier communication control bit PLM_SSC (EXT_CFG.0 = 1, INT2 is used as the interrupt of the carrier communication synchronization signal.

③ When the carrier transmit and receive control bit PLM_RS (EXT_CTRL.0) = 1, the carrier controller is in the transmitting state; when PLM_RS (EXT_CTRL.0) = 0, the carrier controller is in the receiving state.

④Carrier transmission reset register: It is used to prevent the carrier communication module from being in the transmission state for a long time, which makes the entire communication system out of control. It is a 13-bit counter. When in the transmission state, the counter decreases rapidly. After it decreases to 0, the carrier transmission mode is forced to return to the receiving state; in the receiving state, the counter stops working. When sending data for a long time, it is necessary to write "A2H" to the PLM_RST register. After writing, the counter is automatically reset and keeps sending.

The principle structure block diagram of low-voltage power line carrier communication is shown in Figure 4. It needs to cooperate with the peripheral power amplification and receiving circuits. The distance of carrier communication is closely related to the quality of peripheral circuit design and power size.

3. Software Design for Receiving and Sending

Carrier communication is bus communication, so the normal state of the carrier module must be set to receive mode, and different carrier modules must be assigned different communication addresses. After the module receives the command with the correct verification, only the module with the same address is allowed to respond according to the protocol. Since the carrier communication rate is much lower than the main frequency, in order to improve CPU efficiency, reception and transmission are generally designed to be processed in external interrupt mode; each time an interrupt is entered, the reception or transmission of 1 bit of data is completed.

After configuring the module according to the process shown in Figure 3 and selecting the rate as 500bps, the internal PN code is automatically selected as 15 bits. The carrier communication controller enters the receiving state to capture and synchronize the carrier signal.

When receiving, the capture and synchronization process is automatically completed by the hardware circuit of the carrier communication control unit, and no software participation is required. Since the cry of the power line always exists, a synchronization frame header must be added before the valid data. According to the correlation standard, 0x09 and 0xAF are selected, followed by the valid data body and check byte of the communication.

Figure 5 is a flowchart of the carrier communication receiving process. After the carrier communication control unit de-spreads 1 bit of data, an interrupt is generated. When receiving, the 16-bit receiving window and 1-bit sliding mode are first used to receive the communication synchronization frame header 0x09, 0xAF. After the frame header is successfully received, the subsequent data is intercepted in the form of one byte per 8 bits to obtain the valid data for transmission. During the receiving process, address discrimination, length reception, and check calculation are performed according to the relevant communication protocol. The module with the same address responds to the data that conforms to the communication protocol and enters the sending state. Figure 6 is a flowchart of the carrier communication sending process. It is used for the caller of the carrier communication to issue a command or the receiver to respond. When set to the carrier sending state, the carrier communication control unit automatically generates an interrupt after sending 1 bit of spread spectrum data, allowing the next data to be sent. According to the needs of the capture and synchronization process, at least 40 bits of all "1" are sent first; then the synchronization frame header 0x09, 0xAF are sent bit by bit; then the communication address, data length, data body, check and other bytes are sent bit by bit according to the user's relevant communication protocol.

After all data is sent, the carrier module can enter the receiving state. However, to ensure that the last bit of the data to be sent is sent successfully, the carrier transmission state can only be switched to the receiving state after the last bit of data is sent and the next transmission interrupt arrives.

Before the carrier is sent and all data are sent, the CPU must write "A2H" to the PLM_RST register in time to reset the counter to avoid automatic reset and early entry into the carrier receiving state. The sending interrupt program is as follows:

void PLM_int(void)interrupt 7//Carrier transmission and reception interrupt

{if(PLM_RS==1)zb_tx();//Carrier transmission interrupt service routine

else zb_rx()；//Carrier receiving program service program, omitted

}

void zb_tx(void)//Carrier transmission program

{if(len8==0)s_byte=buf_send[zbs_count]; //Get the bytes to be sent and send them to the buffer

ACC=s_byte;

P3.7=ACC^7; //bits sent, the highest bit first

s_byte=s_byte<<1; //left shift

len8++; //Shift count calculation

if(len8>7) //8 bits sent

{zbs_count++; //next byte

len8=0; // shift count cleared

}

PLM_RS=1; //Carrier transmission is allowed

PLM_RST=0xA2; //Carrier transmission reset register cleared

}

Conclusion

The smart meter with carrier communication function designed by SoC chip PL3105 has been applied and promoted in the smart meter industry. Its simple receiving and transmitting processing methods make application design very convenient. At the same time, the flexible ISP programming method makes product upgrading and function expansion flexible; it achieves the design indicators of low cost and high performance.