P87LPC764 uses I2C bus to expand LCD display

1 Introduction
The I2C bus is an inter-chip serial transmission bus introduced by Philips. It uses only two lines, the serial data line (SDA) and the serial clock line (SCL), to achieve perfect full-duplex synchronous data transmission, and can easily form a multi-machine system and peripheral device expansion system.

This article introduces the circuit design method of using the typical LCD driver control device PCF8577C in the I2C bus system to expand the 256-segment static LCD in the P87LPC764 microcontroller.

2 Hardware Circuit Design
2.1 I2C Bus Interface of P87LPC764 MCU
P87LPC764 is a small package, low cost, high performance MCU produced by Philips (for details, see Reference 2). It adopts 80C51 accelerated processor structure and has a hardware interface supporting I2C bus on chip. When I2C bus is activated, P1.2 and P1.3 in port 1 of P87LPC764 can be used as SCL and SDA bus functions respectively. Its I2C bus is controlled by 3 special function registers, namely I2C control register I2CON, I2C configuration register I2CFG, and I2C data register I2DAT. The format and bit meaning of each register are as follows.

a. I2CON Register
The meaning of each bit of the I2CON register is completely different when performing read and write operations. The following describes the read and write operation formats respectively.

The functions of each bit are as follows:

RDAT: Data receive bit. It is acquired from the SDA line at the rising edge of the SCL line. DRDY is not cleared and the SCL line is not released when the RDAT bit is read.

ATN: ATN is set to 1 when any of DRDY, ARL, STR or STP is 1. By testing the ATN bit, it can be determined whether a certain type of event has occurred on the bus.

DRDY: Data ready flag. It is set at the rising edge of SCL and cleared to 0 when reading or writing the I2DAT register or writing 1 to CDR. ARL: Bus arbitration failure flag.

STR: Start flag. Set to 1 when a start condition is detected.

STP: Stop flag. Set to 1 when a stop condition is detected. MASTER: Set to 1 when this device becomes the I2C bus master.

in:

CXA: Write 1 to clear the data sending status.

IDLE: Write 1, and the controlled device will receive bus information only when it detects the next start bit.

CDR: Write 1 to clear DRDY.

CARL: Write 1 to clear ARL.

CSTR: Write 1 to clear STR.

CSTP: Write 1 to clear STP.

XSTR: When the device is the master controller, write 1 to XSTR and CDR to make the I2C bus send a repeated start bit.

XSTP: When the device is the master controller, write 1 to XSTP and CDR to make the I2C bus send a stop bit.

b. I2CFG register
SLA: write 1, the device becomes the I2C bus slave.

MASTRQ: write 1, the device becomes the I2C bus master.

CTI: Write 1 to clear the overflow flag of Timer 1.

TIRUN: Write 1 to start Timer 1; write 0 to stop Timer 1 and clear the timer to 0.

CT1 and CT0 are used to determine the minimum time of high and low levels on the SCL line.

c. I2DAT register

The read and write formats of the I2DAT register are different.

RDAT is the data receiving bit. It is obtained from SDA at the rising edge of SCL line. While reading data from RDAT of I2DAT, DRDY can be cleared and the sending activation status can be set.

XDAT is the data transmission bit. The next data to be transmitted is written to this bit. When writing XDAT, DRDY should be cleared and the transmission activation state should be set.

2.2 I2C bus display device PCF8577C

a. Pin Function

PCF8577C is a typical LCD driver control device in the I2C bus system. It can drive 32-segment LCD in static mode and 64-segment LCD in dual-stage mode. If multiple chips are cascaded, a maximum of 256-segment LCD display system can be constructed. In addition, PCF8577C also has the function of automatically incrementing display data, and programming is very simple. The pin arrangement of PCF8577 is shown in Figure 1. The functions of each pin are as follows:

S32~S1: Segment output port.

BP1: Back-pole output. It can be used as a synchronization input when cascaded, and the BP1 signal of the first stage is used as a synchronization signal.

A2/BP2: In static drive mode, this terminal is used as the hardware address line A2, which is used to set the hardware sub-address of 8577C. In bipolar drive mode, this pin is used as the second back-pole output BP2. In cascade, it is used as a synchronization input, and the BP2 signal of the first stage is used as a synchronization signal. In bipolar mode, its hardware sub-address is determined only by A1 and A0.

A1: Hardware address line. There is no pull-down circuit inside the chip, so it cannot be left floating.

A0/OSC: This pin needs to be connected to an external resistor and capacitor to form an oscillator. At this time, A0 is set to logic 0 and used as a hardware address line. When cascading, except for the first stage, the other stages do not connect to the oscillator composed of resistors and capacitors, but should be connected to VDD or VSS to set the device sub-address.

VDD and VSS: positive and negative power supply respectively.

SCL and SDA: are the clock and data lines of the I2C bus respectively.

b. Data Operation Format

The 8577C has nine registers, and its operation format is shown in Figure 2. The following is an explanation of the control register and segment byte register.

●Control register
The control register is used to load the second byte (control byte) during a data transfer from the microprocessor to the 8577C. The meaning of each bit of the control word is as follows:

MODE: Drive mode selection bit, "0" is to select the static drive mode; "1" is to select the bipolar drive mode.

BANK: Data selection bit, "0" is to select the display of body A data, "1" is to select the display of body B data.

V5V4V3: These three bits correspond to the hardware sub-address. If the slave address of the device matches the slave address on the I2C bus, and V5V4V3 = A2A1A0, the device is selected, and the data sent on the bus can be received at this time, and loaded into the segment byte register, otherwise it will be ignored. In the bipolar drive mode, since A2 acts as BP2, V5 is invalid.

V2V1V0: The address bit of the segment byte register SBR is used to determine which SBR the segment data is written to.

V5～V0 can form a segment byte vector SBV, which has an automatic increment function. If multiple segment byte data need to be transmitted at one time, SBV can be automatically increased by 2 (static mode) or 1 (dual-stage mode) after each segment byte data is loaded to load the next data; when cascading, when a 8577C is full, SBV automatically increases and points to the SBR of the next 8577C with an adjacent hardware subaddress. The value of SBV can be cyclically rolled between 111111 and 000000.

●Segment Byte Register SBR

The eight SBRs can be divided into two groups. The group with even addresses is called A-bank and the group with odd addresses is called B-bank. In static mode, either A-bank data or B-bank data is displayed. The display content can be switched by changing the value of the BANK bit. In bipolar mode, the eight SBRs will be used at the same time. At this time, BANK is a don't care code. A-bank corresponds to BP1 and B-bank corresponds to BP2.

c. Bus operation

The bus operation of PCF8577C includes slave address and hardware sub-address. The slave address is fixed to 0111010, a total of seven bits, which is allocated by the I2C bus committee. In addition, there are three hardware sub-addresses (A2A1A0) to be set. If there are multiple 8577Cs in the application system, different hardware sub-addresses need to be set to distinguish them. Selecting 8577C means that both its slave address and hardware sub-address are selected.

Among them: the lowest bit in the first byte after the start signal S is the direction bit. Since 8577C can only receive data, this bit must be 0; the remaining seven bits are slave addresses. If the system contains multiple 8577C chips, each chip will respond to the first and second bytes; and the response signal after the segment data byte is only generated by the selected chip. There can be multiple consecutive data bytes. If only the BANK value is changed without changing the content in SBR, the stop signal P should be sent after the response bit of the control byte, and the selected chip will update the BANK.

2.3 Display circuit design

The interface circuit for expanding LCD using P87LPC764 is shown in Figure 3. This circuit uses static drive mode, and the P87LPC764 microcontroller accesses 8 8577Cs to form a maximum cascade system. Each 8577C can drive 32 segments of LCD, so a total of 256 segments of LCD can be expanded. In cascade application, only the first stage constitutes the oscillator to output the back pole signal and synchronize the subsequent stage.

3 Software Design

This application circuit is a single-master I2C bus system. The data transmission operation is only the master transmission mode, so there is no bus error detection during the programming process. When sending data, the response signal should be detected for each byte sent. If there is no response signal, the flag F0 is established to resend the data. This circuit uses a static mode and displays A-body data.

If the display buffer 30H to 7FH units in the program are used to store font codes, the program list of the I2C bus display circuit is as follows:

4 Conclusion

This article introduces the circuit and program design of expanding LCD display using typical LCD driver control device PCF8577C in I2C bus system. With reference to the ideas in this article, dynamic LCD display expansion can also be realized. This method has good reference value when designing human-machine interface circuit in I2C bus system.