Applied Materials achieves breakthrough in 3-nanometer chip wiring

Applied Materials achieves breakthrough in chip wiring, driving logic scaling to 3nm and below

• Integrates seven process technologies into one system under vacuum conditions to halve interconnect resistance

• New materials engineering solutions improve chip performance and reduce power consumption

• Latest system demonstrates Applied Materials’ strategy to become a PPACt enablement company™ for its customers

SANTA CLARA, Calif., June 16, 2021 – Applied Materials, Inc. has introduced a new advanced logic chip routing process technology that can scale to 3 nanometer technology nodes and below.

Applied Materials' new Endura® Copper Barrier Seed IMS™ solution integrates seven different process technologies into one system under high vacuum conditions, resulting in improved chip performance and power consumption.

While shrinking transistors improves performance, the effect on interconnect wiring is exactly the opposite: the thinner the interconnects, the greater the resistance, resulting in reduced performance and increased power consumption. Without breakthroughs in materials engineering, interconnect via resistance will increase 10 times from the 7nm node to the 3nm node, offsetting the advantages of transistor shrinking.

Applied Materials has developed a new material engineering solution called Endura® Copper Barrier Seed IMS™. This integrated material solution integrates seven different process technologies, including ALD, PVD, CVD, copper reflow, surface treatment, interface engineering and metrology, into one system under high vacuum conditions. Among them, ALD selective deposition replaces ALD conformal deposition, eliminating the original high-resistance barrier layer at the through-hole interface. Copper reflow technology is also used in the solution to achieve void-free gap filling in narrow gaps. With this solution, the resistance of the through-hole contact interface is reduced by 50%, chip performance and power are improved, and logic scaling can continue to 3 nanometers and below.

“There are tens of billions of copper interconnects in each smartphone chip, and the wiring alone consumes one-third of the chip’s power,” said Perab Raja, senior vice president and general manager of Applied Materials’ Semiconductor Products Group. “Combining multiple process technologies under vacuum conditions allows us to redesign materials and structures to give consumers more powerful devices with longer battery life. This unique integrated solution is designed to help customers improve performance, power and area costs.”

The Endura Copper Barrier Seed IMS system is now in customer production at leading logic node foundries around the world. More information about this system and other logic scaling innovations was discussed at Applied Materials’ 2021 Logic Masterclass on June 16, 2021.

About Applied Materials

Applied Materials, Inc. (NASDAQ: AMAT) is a leader in materials engineering solutions that power nearly every new chip and advanced display produced worldwide. With technologies that can transform materials at the atomic level at scale, we help our customers realize what’s possible. At Applied Materials, we believe that our innovations enable a better future.