Design of Area Array CCD Driving Circuit Based on FPGA

0 Introduction
CCD (Charge Coupled Devices) is a new type of semiconductor integrated optoelectronic device developed in the early 1970s. In the past 30 years, the research on CCD devices and their application technologies has made rapid progress, especially in the field of image sensing and non-contact measurement. It has the advantages of low noise, wide spectral response, high accuracy and sensitivity, and good reliability. The CCD imaging system is mainly composed of an optical system, a drive circuit, a signal processing circuit, and an image processing circuit.
This article mainly introduces the design of the CCD sensor drive circuit, including the drive timing generation circuit, the power conversion circuit, and the driver circuit. Among them, the drive timing generation circuit provides the CCD sensor with various timing pulses required for normal operation; the power conversion circuit provides the CCD with various DC bias voltages required for normal operation; and the driver circuit is used to improve the driving ability of the drive timing.

l Requirements and implementation of CCD drive timing circuit
1.1 CCD image sensor TH7888A
The CCD image sensor uses ATMEL's TH7888A. It is a high-performance frame transfer area array CCD device, providing single-channel and dual-channel output modes, with an output data rate of up to 40 MHz and 30 frames per second. TH7888A has low dark current and pixel readout noise, and can use electronic shutter to adjust exposure time, with excellent performance. TH7888A consists of a photosensitive area, a storage area and a horizontal shift register, with an effective number of pixels of 1 024×1 024.
A working cycle of CCD can be divided into two stages: light integration stage and charge transfer stage. The light integration stage is used to accumulate the charge of the photosensitive array, transfer the charge from the storage area to the transfer register (row reverse process), and output the charge from the transfer register to the output amplifier (row forward process); the transfer stage is mainly used for frame transfer, that is, transferring the light integrated charge of the photosensitive area to the storage area. To complete the above functions, it is necessary to provide a strict driving timing clock to the CCD. The driving timing relationship of TH7888A is shown in Figure 1.

In Figure 1, φPA is the frame clock. When it is high, it is the light integration stage, and when it is low, it is the charge transfer stage. φP1~φP4 are frame transfer pulses, which remain unchanged during the light integration stage, and complete the transfer of the entire frame together with the line transfer control signals φM1~φM4 during the charge transfer stage. In the light integration stage, when the line is in the reverse state, the signal charge of each line in the frame storage area is shifted one line toward the horizontal shift register under the control of the line transfer signals φM1 and φM4, and the readout register clocks φL1 and φL2 remain unchanged; when the line is in the forward state, the pixel charge in the horizontal shift register is output through the output amplifier one by one under the control of the readout register clocks φL1 and φL2. Each time a line of signal is read out, a line transfer is performed. After a frame of image is transferred, the frame transfer of the next frame of image is performed.
1.2 Implementation of CCD drive timing based on FPGA
The programmable logic device FPGA has the characteristics of high integration, high speed, good reliability and hardware programmability. It is flexible to develop, easy to maintain, and very suitable for the design of CCD drive. The design uses the XC3S50 of the Spartan3 series of Xilinx. Based on the analysis of the CCD drive timing relationship, the hardware programming language VHDL is used to write the program, and the development software is ISE 10.1.
The program input is a 40 MHz main clock CLK, provided by an external crystal oscillator, and the output is thirteen drive signals. The design adopts a single-channel output method, and the output data rate is selected as 10 MHz. All 1 024×1 024 effective pixels are used. In the horizontal direction, the effective pixels plus isolation pixels, black reference pixels, etc., total 1 056 pixels. In the vertical direction, the effective pixels plus dummy pixels, black reference pixels, etc., total 1 056 rows. An appropriate amount of redundancy design is performed, and the time occupied by frame transfer and line transfer is considered. The frame rate is 8 frames per second. The reset clock OR is obtained by dividing the main clock by four. Since the timing relationship between the CCD drive signals must be strictly met and the waveform is relatively complex, the program is implemented in a multi-process, multi-counter loop nesting manner. The frame clock φA is the outermost loop. In the light integration stage, the first part of the inner loop is composed of the reverse and forward lines, which is completed by the master clock frequency division and counting design. At the same time, a line pulse signal is generated, and the frame period is generated by counting the line pulse signal. In the charge transfer stage, the frame transfer pulses φP1~φP4 (line transfer control signals φM1~φM4) constitute the second part of the inner loop. The timing relationship between the signals is realized by the master clock frequency division and shifting.
In the design, the following two points need to be noted:
(1) The duty cycle of the frame transfer pulses φP1~φP4 is 5:3, so an octal counter is used to design a pulse with a duty cycle of 5:3, and then the control and shift operation of the frame clock φA are used to achieve its strict timing.
(2) For φA and φP1~φP4, the manual has restrictions on the edge change time of their waveforms. For the upper limit of the time, since the signal is driven by the driver EL7212 after being output from the FPGA and then sent to the CCD, the maximum value of the rise and fall time of the EL7212 output waveform has met this upper limit requirement; for the lower limit of the time, the steepness of the waveform edge can be adjusted by adding capacitors and resistors near the CCD pin to meet the requirements.
1.3 Simulation of CCD drive timing
The design uses the simulation tool provided by ISE 10.1 to simulate the timing, and configures and downloads the FPGA chip XC3S50 of Xilinx Company, and verifies the feasibility of the design through functional simulation. The simulation results of the drive timing are shown in Figures 2 and 3.

As can be seen from the figure, the design has completed the CCD's requirements for driving signals.

2 Power conversion circuit
The working voltage of the CCD circuit is taken from the secondary power supply. The circuit requires a wide variety of voltages, such as the CCD sensor requires a +15 V power supply and a variety of bias voltages, the CCD driver requires +12 V, +9 V, +8 V, +4 V power supplies, and the FPGA requires 3.3 V, 2.5 V, 1.2 V, etc. for normal operation. In order to reduce the types of secondary power supplies and take into account the commonality with other component power supplies, the camera system uses two secondary power supply modules: +15 V and +5 V. The above voltages are all converted from these two power supplies. In order to ensure the stability of the FPGA chip, its voltage is provided by Xilinx's dedicated power conversion chip. The core device for power conversion of other various bias voltages is LMll7. LMll7 is a positive three-terminal adjustable voltage regulator. This voltage regulator has good voltage regulation performance and also has short-circuit protection, overcurrent protection and temperature protection functions.

The output voltage range of LMll7 is 1.2～37V, and the maximum load current of H package is 0.5A. Its linear regulation rate and load regulation rate are better than those of standard fixed voltage regulators. Usually, no external capacitor is required at the input of LMll7, unless the connection line from the input filter capacitor to the input of LMll7 exceeds 15cm. Figure 4 is the schematic diagram of realizing DC bias +12V. In the figure, the voltage reference between pins 2 and 3 is 1.25V, and the regulated voltage value can be adjusted by changing the resistance value of R2. The output voltage is:

Where: I is the current flowing through R1 and R2. Here, the current consumed by the ADJ control terminal of LMll7 is very small and can be ignored. Therefore, . Here, the resistance values ​​of R1 and R2 cannot be set arbitrarily. First, from the voltage variation range of 1.25 to 37 V, it can be seen that the ratio range of R2/R1 is 0 to 28.6; secondly, LMll7 has a minimum stable working current, which is generally 1.5 mA. If it is lower than this value, the loaded voltage and no-load voltage output by the voltage regulator may differ greatly. Therefore, by setting the resistance values ​​of R1 and R2 to ensure that V0/(R1+R2)≥1.5 mA, LMll7 can work stably when no-load. The design selects R1 resistance value of 240 Ω, and R2 can be calculated. R2 uses a potentiometer for easy debugging; diodes D1 and D2 are used to protect LMll7; output capacitor C1 can change transient response; the use of filter capacitor C2 at the adjustment end can obtain a higher ripple suppression ratio than the standard three-terminal regulator.

3 CCD driver
The function of the CCD driver part is to power amplify the various transfer pulse signals output by the CCD timing generation unit to meet the CCD's requirements for driving waveform voltage, current and timing. The quality of the driving signal will have a great impact on the charge transfer efficiency of the CCD, thus affecting the quality of imaging. In the design, there are 13 driving signals and reset signals required for the normal operation of the CCD. There are 4 voltages of these signals. Different voltages are converted and output by the power converter LMll7 mentioned above, and then enter the driver chip to drive the driving signal and reset signal. Since the CCD is a capacitive load, it is necessary to provide a sufficiently large transient driving current when the voltage swing is large, so a device with a large enough working current should be selected to meet the requirements. The chip selected is Intersil's EL7212. Compared with the commonly used ICL7667 and DS0026, EL7212 performs better in speed, driving ability, response time, noise suppression, etc. Its rising and falling edges change faster, and the typical value is 10/13 ns when the capacitive load is 1 000 pF, which is more suitable for high-speed cameras. EL7212 works in a single power supply mode, and its application circuit is shown in Figure 5. In Figure 5, resistor R1 is used to reduce internal power consumption, resistor R2 and capacitor are used to prevent overshoot, and the capacitor is as close to the pin as possible.

4 Conclusion
Based on the analysis of the working principle and driving signal requirements of the area array CCD sensor TH7888A, a reasonable driving signal timing is designed using programmable logic device FPGA and hardware description language VHDL, and high-performance voltage conversion chips and drivers are selected to ensure the normal and stable operation of CCD. The experimental results show that the designed CCD driving circuit meets the working requirements of CCD well.