Understanding Multi-core DSP C6678 Shared Memory Issues

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Understanding Multi-core DSP C6678 Shared Memory Issues [Copy link]

Generally speaking, the default configuration is L2. Users can decide whether to configure it as L3 based on their own applications. The most common scenario for setting MSMC to L3 is: MSMC memory needs to be non-cacheable, and MSMC needs to be set to L3 RAM. MSMC is configured as L2 by default, and can be configured as L3 based on user needs. Since configuring it as L3 only does address mapping, the physical access time should still be an order of magnitude, with little difference. The difference between L2 and L3 here should be that L2 can only be cached by L1D and L1P, while L3 can be cached by L2, L1D, and L1P. The MSMC of C6678 is responsible for processing access requests to MSMC SRAM and DDR3 from all masters in the system (including 8 cores, as well as SMS and SES interfaces). The 4M-byte MSMC SRAM has 4 banks, which are independent slaves. That is, if two masters access two different banks at the same clock, the two accesses can be completed at the same time. If multiple masters access the same bank at the same clock, the arbitration logic in the MSMC will handle it according to priority. DDR3 has only one slave port. If multiple masters access it at the same clock, the arbitration logic in the MSMC will also handle it according to priority. MSMC is configured as L2 by default, and can be configured as L3 according to user needs. Since configuring as L3 only does address mapping, the physical access time should still be an order of magnitude, with little difference. The difference between L2 and L3 here should mean that L2 can only be cached by L1D and L1P, and L3 can be cached by L2, L1D, and L1P. Generally speaking, the L2 configuration is used by default. Users decide whether to configure it as L3 based on their own applications. The most common scenario where you need to set MSMC to L3 is when you need MSMC memory to be non-cacheable and you need to set MSMC to L3 RAM.