Correction process of stabilization time circuit

Corrections Settling Time The circuit can achieve the performance it claims. These corrections can be roughly divided into four predetermined categories. They are: current switch bridge drive pulse shaping, circuit delay, sampling gate pulse purity, and sampling gate feedthrough/dc adjustment. Correction work requires quite careful instrument selection and careful broadband probing and oscilloscope measurement techniques.

Bridge driver correction

First, the current switching bridge drivers must be corrected. Disconnect all five bridge drivers involved in the correction and apply a 5V, 1MHz, 10ns-15ns wide pulse to the circuit input. The output of the parallel "C" inverter seen at the undriven end of the 43V rear end should look like this. The edge times of the waveform are fast, but if parasitic offsets are not controlled well, there is a danger of corrupting the measurement noise background, and they must be eliminated. Reconnect all five drivers and make adjustments according to their respective names. There should be some interaction between the various adjustments.

Determination and compensation of delay

Next is the circuit delay. Before making these measurements and adjustments, the probe/oscilloscope channel-to-channel skew must be corrected. When the probes of both channels are connected to a fast pulse source with a 100ps rise time, there is a 40ps skew error. There are many fast pulse sources that can be used. The method to correct for this error is to use the oscilloscope's vertical amplifier variable delay function. In this case, the oscilloscope amplifier is a TektrONix 7A29, option 04, installed in a Tektronix 7104 rack. This correction allows you to make high-precision delay measurements. The accuracy of the oscilloscope's time base should also be verified.

The settling time circuit uses an adjustable delay network to correct for the delay of the input pulse in the signal processing path. Typically, these delays will introduce errors of nearly 10ns, so an accurate correction must be provided. The delay correction operation involves observing the input/output delays of the network and making appropriate time interval adjustments. Sometimes, determining the appropriate time interval is more complicated.

There are three delay measurements of interest in the circuit. The current switch driver delay at the negative input of the amplifier under test, the output delay of the amplifier under test at the output of the circuit, and the delay of the sampling gate multiplier. The current switch driver delay at the input of the amplifier under test is 250ps, the delay from the output of the amplifier under test to the output of the circuit is 8.4ns, and the delay of the sampling gate multiplier is 2ns.

These measurements show a current switch driver delay of 8.65ns at the output of the circuit. This correction is accomplished by adjusting the 1kV potentiometer in the “Signal Path Delay Compensation” network. When using a sampling oscilloscope for measurement, this is adjusted into the signal path delay compensation network.

The “sampling gate generator path delay compensation” is less critical. The only requirement is that it overlaps the delay of the sampling gate generator. Setting the 1kV potentiometer in the “A” inverter chain to 15ns meets these criteria. This completes the delay-related correction.

Purity adjustment of sampling gate pulse

The pulse edge shaping stage of the Q1 sampling gate is adjusted to obtain an optimized leading corner, minimum rising edge time, smooth pulse top, and a specified corrected 1V amplitude. The adjustment is observed at the "X" input of the sampling gate multiplier IC. The second rise time of the pulse promotes fast sampling gate acquisition, but still stays within the 250MHz bandwidth of the multiplier, ensuring no out-of-band spurious response. The clean 1V pulse provides a corrected, continuous multiplier output without spurious (which could masquerade as a stable signal). The pulse fall time is irrelevant and has no bearing on the measurement, while its clean falling transition ensures the shutdown of the controlled multiplier and prevents background excursions.

Optimization of sampling gate path

The sampling gate path adjustment is the last item. First, place 5Vdc at the pulse generator input to lock the amplifier under test into its 22.5V output state. Then adjust the "stable node null" tap to get zero volts to within 1mV at the output of A1. Next, restore the input of the pulse circuit, disconnect the stable node from A1, and connect the input of A1 to ground with a 750Ω resistor. The response before adjustment is not ideal. Ideally, the circuit output (Trace B) should remain static during the switching of the sampling gate (Trace A). The photo shows the error; correction requires adjustment of dc offset and residuals related to dynamic feedthrough. Adjusting the "X" and "Y" offsets of a continuous Trace B reference line (independent of the sampling gate pulse state of Trace A) can eliminate the dc error. In addition, the adjustment of the output offset is set for the lowest multiplier reference offset voltage. The sampling gate can be set to unity gain by turning off the input pulse generator, applying 5V to the "1" input of C2, and biasing it at 1.00Vdc with the 750Ω resistor inserted earlier. Under these conditions, the "scale factor" is adjusted for a 1.00Vdc output. After this step is completed, the dc bias voltage and 750Ω resistor are removed, the stable node is reconnected, and the pulse input is restored.

Compensation for feedthrough is done using the “Time Phase” and “Amplitude” adjustments. These adjustments set the timing and amplitude of the feedthrough correction applied at the “Z” input of the multiplier IC.

Limitations and Uncertainties of Measurement

The corrected response of the circuit includes a flat reference and significantly attenuated feedthrough. The measurements define the circuit's minimum amplitude resolution of 2 mV. For other tests, the A1 input was disconnected from the stable node and biased at 20 mV through a 750 Ω resistor to simulate an infinitely fast settling amplifier. The circuit output (Trace B) settles to within 5 mV in 2 ns and reaches within 2 mV of the reference noise in 3.6 ns. This data is taken at the time when the sampling gate is just turned on, after the time-corrected input (Trace A) rises, and defines the circuit's ultimate minimum time resolution. The uncertainties in the quoted time and amplitude resolution limits are primarily due to delay compensation limitations, noise, and residual feedthrough. Considering possible delay and measurement errors, the 6500 ps uncertainty and 2 mV resolution limit are realistic. Noise averaging does not improve the amplitude resolution limit because it is an inherent term from feedthrough residuals.