Design of controller for LCOS of different specifications based on SOPC

Abstract: By building a soft-core processor (NIOSⅡ) in a field programmable gate array device to replace a dedicated integrated circuit, and embedding a C program in NIOSⅡ, the calculation of various design parameters at different scales is automatically realized according to the given scale. The design of LCOS controllers that can be applied to different scales by only inputting system parameters is realized, and the applicability and reliability of LCOS controllers are improved by combining USB chips and specific program flows, and the cost of devices is reduced.

1 Introduction

As the core component of adaptive optical systems, the corrector determines the development direction of adaptive technology to a large extent. At present, the deformable mirror corrector is widely used in adaptive optical systems.

With the use of adaptive technology in fundus observation, the traditional deformable mirror corrector reveals its inherent shortcomings. Due to the limitation of few correction units, it is difficult for the deformable mirror corrector to image the fundus with high-order aberrations. Therefore, liquid crystal correctors with more correction units have begun to be widely used in the field of fundus observation. Compared with glass substrate liquid crystal displays, liquid crystal displays (LCOS) using silicon substrates have become the best choice at present due to their advantages such as small size, high resolution, and high light efficiency. As the core of the LCOS driving circuit, the LCOS controller that provides display data and timing signals for the liquid crystal module (LCM) is usually composed of an application-specific integrated circuit (ASIC). In actual engineering applications, LCOS of various resolutions are required. Since each LCOS requires a dedicated display controller, the design and use of LCOS are relatively cumbersome.

This design uses field programmable gate array (FPGA) devices to replace ASIC, and uses programmable system on chip (SOPC) to implement the design of a universal LCOS display controller. In use, the control of LCOS with different resolutions can be completed by simply modifying the software parameters. Since the amount of data that the liquid crystal adaptive system needs to transmit is large, in order to ensure the real-time performance of the system, the USB2.0 protocol is used for data transmission. This paper uses the USB chip PDIUSBD12 of NXP and the EP1C6Q240C8 device of ALTERA, and uses C++ language to design the USB driver and firmware program. The universal LCOS controller is designed using VHDL hardware description language and passed the test in actual application, basically achieving the expected goal of the universal LCOS controller.

2 System Principle

LCOS displays in a row-by-row scanning mode, that is, when a row is selected, the signals of each column in this row are added to the column at the same time and maintained for a scanning row. When this time is over, the next row is selected, and the display voltage of the next row is applied to each column electrode.

At present, ordinary liquid crystal controllers are composed of memory and controller. An MCU receives the display data sent by the host computer, and the MCU allocates the storage address, generates the timing signal, stores the data in the memory, and then the liquid crystal display module reads the data in the memory. The access speed of the memory is slow, and it is very time-consuming to read and write large quantities of data. It is difficult to match the response speed of LCOS, and when replacing the LCOS display module with different resolutions, a new controller is required, which has the disadvantages of high cost and cumbersome process.

In view of this, this paper proposes the idea of ​​designing LCOS controller based on SOPC, that is, building a NIOSⅡ soft-core processor and SRAM memory in FPGA, mapping SRAM to the data buffer of LCOS display module, connecting NIOSⅡ to PDIUSBD12 in DMA mode, connecting NIOSⅡ to the host computer in serial port mode, and adapting to LCOS with different resolutions by setting various parameters including LCOS parameters and memory scale parameters; saving transmission time by DMA mode; saving memory access time by mapping SRAM to display data buffer. As shown in Figure 1.

LCOS system schematic diagram

Figure 1 LCOS system schematic diagram.

3 System Design

3.1 System Pin Signal Timing Analysis

Generally speaking, the LCM pins have the functional description shown in Table 1.

Table 1 LCM Pin Signal Function

LCM Pin Signal Function

Each CP shift pulse signal stores a complete row of display data (D0~D7) into the shift register through a series of CP pulses. The shift register is connected to the latch in parallel. When a complete row of display data is stored in the shift register, the row data is latched into the latch under the action of the latch signal LP and output to the column electrode. Therefore, the cycle of LP should be one row cycle. When the last row of display data of a frame image is stored in the shift register, the FLM frame scan signal becomes a high level, and its pulse width maintains more than one LP pulse width. Therefore, the cycle of FLM should be the time of a frame image, that is, the sum of the cycles of each row LP. M is the AC drive signal of the liquid crystal display module. The polarity of the waveform is changed once every frame time, which can prevent the unidirectional distortion of the liquid crystal display. More detailed pin signal timing relationships are shown in Figures 2 and 3.

Timing relationship of pin signals 1

Figure 2 Timing relationship of pin signals 1.

Figure 3 Timing relationship of pin signals 2.

3.2 Parameter determination

Before designing a general-resolution LCOS controller, some parameters must be determined. These parameters include the resolution of LCOS m×n, the grayscale of LCOS 2u (generally, the grayscale of LCOS is 256), the refresh frequency of LCOS display a Hz, the frequency of signal CP b MHz, etc. These parameters are sent to the NIOSⅡ processor by the host computer through the serial port. According to these parameters, NIOSⅡ calculates the following relationship: the period of each frame is 103/a (ms); the period of each line is 106a-1 n-1 (us); the time to write a line of display data into the register is m/b (μs); the empty time of each line is [106a-1n-1]-[m/b]u s), which should be no less than 0. Based on the calculated data and the signal relationship shown in Figures 2 and 3, a timer and a pulse width modulator (PWM) are used to generate the logic control signal of LCOS. Similarly, the design of SRAM memory must be completed in NIOSⅡ. The implementation of memory is realized by the logic gate array in FPGA. The principle followed by the design is that the capacity of SRAM can at least hold 2 complete frames of data, that is, 2m×n×2u. One frame of data storage area is used for current display, and the other frame of data storage area simultaneously receives the data to be displayed in the next frame. Although such a strategy consumes a large number of logic gates, it can match the low-speed memory with the high-speed LCOS display, and better play the speed advantage of USB.

4 Example Design

In practical applications, the LCOS controller is designed by taking the LCOS with 256×256 resolution and 256 gray levels as an example.

First, various parameters are calculated based on the existing LCOS. For the 256×256 LCOS, its refresh frequency is 200Hz, and the frequency of the clock signal CLKB is 20MHz. Therefore, the cycle of each frame is 5ms, the cycle of each line is 19.53μs (equivalent to 391 CLKB clock cycles), the time to write a line of display data into the register is 12.8μs (equivalent to 256 CLKB clock cycles), and the empty time of each line is 6.73μs (equivalent to 135 CLKB clock cycles). If it is found that the empty time of each line is less than 0 during design, the frequency of the clock signal CLKB should be increased.

The next step is to design the SRAM memory. The design principle of the SRAM capacity is to be able to hold a complete 2-frame data, that is, 2×256×256×256 can hold a complete 2-frame data. However, in order to facilitate the CPU to complete other calculations, the memory design should be larger than 2 frames of data. Here, the capacity of 3 frames of data is taken, and a fixed area is set as the display buffer.

The USB data input buffer is also set in the display buffer area, so that the data to be displayed input through the USB port is directly stored in the display buffer area.

Then, the data input port of the external LCOS display is used as the I/O mapping address of the NIOSⅡ processor. Through DMA processing, the display buffer of the NIOSⅡ memory is directly input through the AHB bus and the data input port of the LCOS display in DMA mode. The advantage of using DMA and bus is that it is simple and fast, and the transmission is very stable.

The functional simulation test of the NIOSⅡ controller is carried out in the QuaartusⅡ6.0 environment, and the simulated waveform is shown in Figure 4. The timing signal of the controller meets the design requirements. After completing the functional simulation, the gate-level netlist is generated through synthesis and downloaded to the Cyclone series EP1C6Q240C8 device of ALTERA.

Functional simulation waveform of NIOSⅡ controller

Figure 4 Functional simulation waveform of NIOSⅡ controller.

5 Conclusion

A LCOS universal controller is designed using SOPC and USB. Usually LCOS is expensive and not universal. The method in this paper can minimize the material cost and design cost, and can be adapted to different LCOS displays by sending different parameters according to the needs of the application. Due to the use of soft-core processor, the stability of the system is slightly worse, and the speed of PDIUSBD12 is only 12MB/s. In order to improve the stability of the system, an ARM9 processor can be used; in order to give full play to the full speed of USB2.0 480MB/s, a new generation CH375USB controller can be used. In this way, the LCOS universal controller can have better performance.