Design of Multi-Network-Port Card Based on CPCI Bus

Ethernet has emerged as the most widely used LAN technology and has quickly moved to the forefront of industrial automation control. CPCI bus system slots are limited, and designing a multi-port card based on CPCI bus can save space and meet the real-time and large data transmission requirements of status monitoring and fault diagnosis systems.

1. Module overall design

The module is designed with CPCI parallel bus. Figure 1 shows the overall design block diagram of the module, where four INTEL82551s are connected via PCI bridge expansion bus. Since INTEL82551 has integrated PCI interface, PCI bridge can achieve seamless connection with INTEL82551. J1 and J2 are CPCI interface plug-ins.

2CPCI bus structure module

2.1 Principle and structure

If too many electrical loads or devices are connected to a PCI bus, the bus will not work properly. The problem can be solved by adding one or more additional PCI buses to the system. The only way to expand another PCI bus in the system is to use a PCI-PCI (P2P) bridge for system expansion. A P2P bridge is a special PCI device that can glue the PCI buses in the system together. A P2P bridge connects the master and slave PCI buses in the system. It acts as a load on the upper bus and can drive a bus segment downward by redriving and arbitrating the PCI signals.

Its role is to coordinate data transfer between the two PCI buses, monitor all transactions initiated on the two PCI buses, and decide whether to transfer the transaction through the other PCI bus. When the bridge determines to transfer a transaction on one bus to another bus, the bridge must act as the bus target of the transaction bus and the master device of the destination bus of the transaction. System designers can also install multiple P2P bridges.

2.2 PCI2050B Introduction

According to the characteristics of system integration, TI's PCI2050B bridge is selected here to implement the P2P bridge. PCI2050B is a transparent PCI-PCI bridge that provides a bridge connection between two 32-bit PCI buses with a maximum operating frequency of 66MHz. The bridge supports burst mode transfers, which greatly increases the data throughput. The bus data paths of the bridge work independently. The master and slave buses of the bridge can work in 3.3V or 5V environments respectively, while the core logic of the bridge works at 3.3V to reduce power consumption. The host software operates the bridge through internal registers. The internal registers can be used to obtain the status of the standard PCI and control the master and slave buses. The PCI configuration header of the bridge can only be operated through the master PCI interface. PC-I2050B has 9 slave buses. In addition to providing internal arbitration for each slave bus, it can also provide external arbitration for the system. PCI2050B provides 10 slave-side clock outputs.

2.3 PCI Bridge Design

According to the overall design block diagram of the module, the following aspects should be paid attention to in system design.

2.3.1 Clock Design

Figure 2 is a block diagram of the clock design of PCI2050B.

The main points of the clock design are as follows:

1) PCI2050B has two independent clock domains. The master interface is controlled by the master input clock P_CLK, and the slave interface is controlled by the slave input clock S_CLK. These two clocks are independent of each other, but keep synchronization, and the clock frequency of the slave side cannot be higher than the clock frequency of the master side. The maximum delay between P_CLK and S_CLK shall not exceed 7ns, and S_CLK cannot lead P_CLK.

2) The slave side of PCI2050B has 10 clock outputs S-clkout[9:0], 9 of which can be supplied to the extended PCI slots. To ensure clock output synchronization, the other one must be fed back to the input clock S_CLK of the slave side. Each clock can only drive one load.

3) In order to reduce the signal reflection of the clock, the 9 clock outputs to the expansion slot must be matched with series resistors at the starting end. The resistance value of the matching resistor is related to the characteristic impedance of the circuit board. For a 65Ω transmission line, a 50Ω series matching resistor is selected.

4) In order to reduce the jitter (skew) between these clocks, the 9 clock lines (9 S_clkout) supplied to the expansion slot (or expansion device) must be equal in length to S_CLK. Therefore, the length of the clock line fed back from the S_clkout[9] output to S_CLK should be equal to the total length of the clock line from the clock output pin of PCI2050B to the expansion device. This module expands 4 network ports and uses the 4 output clocks from the PCI2050B. In PCB wiring, these 4 clock lines and the feedback clock line must be equal in length.

2.3.2 Interrupt Design and IDSEL Mapping

PCI2050B supports 9 slave devices. When initializing the configuration space read and write, PCI2050B, as the operation object of the upper-level PCI bus, provides an IDSEL pin for device selection. This pin can be connected to any one of the high 24-bit PCI buses. At the same time, in order to reduce the capacitive load of the address line, a 1kΩ resistor needs to be connected in series on the signal line. This module only extends the primary bus. The IDSEL pin on the PCI2050B master side is directly connected to the IDSEL of the CPCI socket J1. For the PCI device on the secondary bus side (INTEL82551 in this module), its IDSEL pin is connected to any one of the S_AD31S_ADl6 pins of PCI2050B through a 1kΩ resistor. The INT line from the device on the slave side does not pass through the bridge. If the bridge is located on an inserted card, the interrupt line of the slave device is directly connected to the interrupt pin (INTA#~INTD#) of the connector. In this module, PCI2050B is a bridge device, and the interrupt pin of INTEL82551 is directly connected to the interrupt pin of J1. The connection of the interrupt line of all slave devices is bound to the device number (that is, the connection of the IDSEL line), and the corresponding relationship is shown in Table 1. The IDSEL pins of the four INTEL82551s are connected to S_AD28, S-AD29, S_AD30 and S_AD31 respectively, and the corresponding device numbers are 12, 13, 14, and 15. The interrupt pin INT# of the device is connected to INTA#, INTB#, INTC#, and INTD# of J1.

2.3.3 PCI2050B working mode selection

PCI2050B has three working modes to choose from: TICPCI hot-swap mode, power management mode and INTEL21150 compatible mode. The selection pins are MSO and MS1 respectively, and the mode selection definition is shown in Table 2.

According to the needs of CPCI bus application design, the author selected TICPCI hot-swap working mode. When PCI2050B selects TICPCI hot-swap working mode, in order to ensure the normal operation of hot-swap logic, it is required to pull up the HS_SWICH/GPI03 pin and HSENUM pin. At the same time, since the GPI0 pin of PCI2050B is not used and these pins are defined as input pins under default conditions, in order to avoid false triggering, all these pins are pulled up.

3 Ethernet ports

This network card uses 4 INTEL82551, 4 EEPROM93C46 and 4 PE68515 to realize 4-way Ethernet network interface. INTEL82551 is a highly integrated Ethernet controller of Intel. Its main function is to realize the sending and receiving of Ethernet frames. It integrates 10Base-T/100Base-TMAC controller and 10Base-T/100Base-TPHY controller, supports full-duplex or half-duplex transmission of data, supports automatic negotiation, supports 10/100Mb/s transmission rate, and supports flow control mechanism.

3.1Interface design between INTEL82551 and PCI bridge

The CPCI bus signal of each INTEL82551 is connected to the slave side of PCI2050B. It should be noted that the signal IDSEL and INT# correspond one to one according to Table 1. Otherwise, the system cannot drive the module correctly when the module is inserted into the system slot. The circuit connection of 1 device is shown in Figure 3. The IDSEL of the device is connected to S_AD31, and the interrupt INT# of the device is connected to INTD# of J1.

3.2 Intel82551 and transmission medium interface

Four PE68515s and four RJ-45s are used to implement the transmission medium interface. Each interface circuit is connected as shown in Figure 4.

3.3 Network card debugging

After the PCB is assembled, check whether there is any cold soldering in the components and other circuits. Insert the network card into the CPCI chassis slot. You can see the module properties in the system device manager. For example, if IDSEL is connected to AD31, the property is PCISLOT1 (PCI bus N, device 15, function O) (N is the bus number). After configuring the network card with EEUPDATE, the module can send and receive data normally.

4 Conclusion

This four-port module complies with PCI2.2 specification and has been successfully applied to the Windows platform of 3UCPCI chassis. It can be expanded to eight-port CPCI card according to needs. This series is based on CPCI multi-port card and can be widely used in various test equipment, wired communication and other fields.