Implementing parallel communication between microcontroller and ISA bus using CPLD

    Abstract: ALTERA company's MAX7000 series CPLD chip is used to realize parallel communication between the microcontroller and PC104 ISA bus interface, and the system design method and program source code are given. Including communication software and AHDL design part.

    Keywords: CPLD ISA bus parallel communication

CPLD (Complex Programmable Logic Device) is a complex user-programmable logic device due to its continuous connection structure. This structure makes it easier to predict delays, making circuit simulation more accurate. CPLD is a standard large-scale integrated circuit product that can be used in the design of various digital logic systems. In recent years, due to the adoption of advanced integration processes and mass production, the cost of CPLD devices has continued to decrease, and the integration density, speed and performance have increased significantly. A complex digital circuit system can be implemented with one chip; coupled with easy-to-use development tools , using CPLD devices can greatly shorten the product development cycle and bring great convenience to design and modification [1]. This article takes ALTERA's MAX7000 series as an example to implement parallel communication between the MCS51 microcontroller and the PC104 ISA bus. Using this communication method, data transmission is accurate and high-speed. In the data acquisition system controlled by the MCS51 microcontroller with a 12 MHz crystal oscillator, it can meet the requirements for real-time communication with the PC104 ISA bus interface, and the communication rate reaches 200 Kbps.

1 Overall system design plan

This system uses CLPD to realize parallel communication between the microcontroller and the PC104 ISA bus interface. Since PC104 mainly completes other aspects of data collection work and can only receive data from the microcontroller when it is idle, the communication between both parties is required to be very real-time, but the amount of data is not very large. Therefore, in the system design, the microcontroller receives data in interrupt mode, and PC104 uses query mode to receive data. The system design scheme is shown in Figure 1.

In the microcontroller part of Figure 1, D[0..7] is the data bus, A[0..15] is the address bus, RD and WR are read and write signal lines respectively, and INT0 is the external interrupt of the microcontroller. When the external interrupt signal of the microcontroller is valid, the microcontroller receives data.

In the CPLD part, it is implemented by an EPM7128LSC84 in the MAX7000 series, which is used to complete data transmission, status query and delay waiting between MCS51 and PC104ISA bus interface.

In the PC104 ISA part, only the 8-bit data bus D[0..7] of the ISA is used, and A[0..9] is the address bus of PC104; IOW and IOR are the read and write signals for the specified device; AEN is the allow DMA controls the address bus, data bus and read and write command lines for DMA transmission, and reading and writing of memory and I/O devices; IOCHRDY is the I/O ready signal, and the I/O channel ready is high. At this time, the processor generates The memory read and write cycle is 4 clock cycles, and the resulting I/O read and write cycle and DMA byte transmission both require 5 clock cycles. MCS51 sets this signal to low level to cause the CPU to insert a waiting cycle, thereby extending the I/O O cycle; SYSCLK is the system clock signal to maintain synchronization with external devices; RESETDR is the power-on reset or system initialization logic and is the system total clear signal.

2 Hardware implementation based on MAX+plus II

This system uses ALTERA's CPLD development tool MAX+plusII. It supports multiple input methods, providing great convenience for design and development. The main part of the system still uses the schematic input method. Since the current chips are provided in the library, it is very convenient to use. The schematic input part is shown in Figure 2 and Figure 3. Figure 2 mainly completes the data transmission and handshake judgment in the communication between the microcontroller and the ISA interface.

D[0..7] 8-bit bidirectional data bus of microcontroller;

PCD[0..7] 8-bit bidirectional data bus of ISA interface;

Read valid signal of PCRD ISA interface;

PCWR ISA interface write valid signal;

Determine whether the microcontroller has written data or read data;

PCSTATE The microcontroller uses this to query the data that has been retrieved by the ISA interface;

MSCRD is the read valid signal of the microcontroller;

MCSWR is the write valid signal of the microcontroller;

INT0 is the external interrupt signal of the microcontroller;

When the MCUWR signal is valid, the microcontroller latches the data in 74LS374 (1). At this time, PCSTATE becomes high level. PC104 uses the STATE signal to strobe 74LS244 to determine whether the data bit PCD0 is high level. If it is high, it means that the microcontroller has sent data, then the PCRD is valid and the data is taken from the data register 74LS374 (1). At this time, PCSTATE becomes low level, and the microcontroller determines that PC104 has taken away the data by judging that this signal is low level, and can send the next data.

When PC104 communicates with the microcontroller, the most critical issue is speed matching. Since PC104 is fast and the microcontroller is slow, a waiting period must be inserted at the IOCHRDY of PC104, as shown in Figure 3.

IOCHRDY is used to make the ISA interface wait for 5 clock cycles;

DLY_D delay input signal;

DLY_CK delays waiting for clock signal;

DLY_CLR waits for the clear signal to prepare for the next data sending cycle;

DELAY is the output signal delayed by 5 clock cycles and serves as the input of the DLY_CLR signal;

SYSCLK System clock signal for the ISA interface.

During the communication process between MCS51 and PC104, the DLY_D signal is always valid (high level). Under the action of signal SYSCLK, the DELAY signal is valid once every 5 clock cycles, that is, high level. At this time, the DLY_CLR signal is valid (low level), the IOCHRDY signal becomes high level, and PC104 can read and write data.

The address decoding part adopts text input mode and uses ALTERA's hardware design and development language AHDL (Altera Hardware Description Language). AHDL is a modular high-level language that is fully integrated into the MAX+plusII system. It is particularly suitable for describing complex combinational logic, state machines and truth tables. The address decoding part uses text input, which fully reflects the text input method. advantages of the method. The text input content is as follows:

SUBDESIGN Address

(

PCA[9..0] : INPUT;

AEN,IOR,IOW : INPUT;

RESETDR,DELAY : INPUT;

A[15..14]: INPUT;

RD,WR : INPUT;

DLY_D : OUTPUT;

DLY_CK : OUTPUT;

DLY_CLR: OUTPUT;

STATE: OUTPUT;

PCRD: OUTPUT;

PCWR: OUTPUT;

MCURD: OUTPUT;

MCUWR: OUTPUT;

)

BEGIN

!DLY_CLR=RESETDR#DELAY;

DLY_D=!AEN & (PCA[9..1]= =H"110");

DLY_CK=!AEN & (PCA[9..1]= =H"110")&(!IOR # ! IOW);

!PCWR=!AEN&(PCA[9..0]= =H"220")& !IOW;

!PCRD=!AEN&(PCA[9..0]= =H"220")& !IOR;

!STATE=!AEN&(PCA[9..0]= =H"221")&!IOR;

!MCSRD=([15..14]= =H"1")& !RD;

!MCSWR=(A[15..14]= =H"2"& !WR;

END;

Note: PCA[9..0] is the address signal of PC104, A[15..14] is the address signal of the microcontroller, and PC104 uses port addresses 220H and 221H.

3 Communication software design

PC104 is based on the ISA bus, and address conflicts must be prevented in system software design. PC104 uses A0~A9 address bits to represent I/O port addresses, which means there are 1024 port addresses: the first 512 are used by the system board, and the last 512 are used by the expansion slot. When A9=0, it represents the port address on the system board; when A9=1, it represents the port address on the expansion slot interface card [2]. Therefore, the reserved port addresses 220H and 221H are used to ensure that no address conflict will occur.

In this program, PC104 uses query mode to receive data, and the microcontroller uses interrupt mode to receive data.

#define pcreadwrite 0x220 /*PC104 read and write data port address*/

#define pcrdstate 0x221 /*PC104 query status port address*/

PC104 write data function:

Void pcwrite(int port,unsigned char ch)

{ outportb(pcreadwrite,ch);

while ((inportb(pcrdstate)&0x02)!=0x02); /*Waiting for the microcontroller to read the data*/

{ }

}

Microcontroller reading subroutine:

MCUWR: MOV DPTR, #4000H

MOVX A, @DPTR

RETI

PC104 read data function:

Unsigned char pcread(int port)

{ while((inportb(pcrdstate)&0x01)!=0x01);/*Waiting for the microcontroller to write data*/

{}

return inportb(pcreadwrite);

}

Write subroutine for microcontroller:

MCUWR: MOV DPTR, #8000H

MOVX @DPTR,A

;Waiting for PC104 to read the data

RET

4 Conclusion

CPLD is used to realize parallel communication between the microcontroller and the ISA bus interface. The circuit structure is simple and the volume is small. One CPLD chip is enough, and the control is convenient, the real-time performance is strong, and the communication efficiency is high. This design method has been successfully used in various data acquisition systems developed by the author, and is used as parallel data communication between the microcontroller and PC104, and the effect is very ideal.