CPLD-based serial-to-parallel conversion and high-speed USB communication design

    Abstract: CPLD programmable technology has the characteristics of high functional integration, flexible design, short development cycle, and low cost. This article introduces the serial-to-parallel conversion and high-speed USB designed based on ATMEL's CPLD chip ATF1508AS and its application in high-speed and high-precision data acquisition systems.

    Keywords: CPLD serial-to-parallel conversion USB

Programmable logic device (PLD) is an epoch-making new logic device developed on the basis of ASIC design in the 1970s. Since the advent of PLD devices, TTL, CMOS, ECL and static RAM technologies have been used in the manufacturing process. Device types include PROM, EPROM, E2PROM, FPLA, PAL, GAL, PML and LCA, etc. The development of PLD in performance and scale mainly relies on the continuous improvement of manufacturing processes. High-density PLD is the product of the highly developed VLSI integration process. In the late 1980s, American ALTERA and XILINX companies used EECMOS technology to launch large-scale and ultra-large-scale complex programmable logic devices (CPLD) and field programmable logic gate array devices (FPGA) respectively. While achieving high integration, this chip has application flexibility and multi-configuration functions that are unmatched by previous LSI/VLSI circuits. Since the 1990s, programmable logic devices CPLD/FPGA have developed rapidly, moving towards high integration, high speed and low price; not only do they have electrical erasability characteristics, but also edge scanning and online programming have appeared. Advanced features; its application areas are constantly expanding and can be used in many aspects such as state machines, synchronization, decoding, decoding, counting, bus interfaces, serial-to-parallel conversion, and its applications in the field of signal processing are also becoming active. Using CPLD can improve system integration, reduce noise, enhance system reliability and reduce costs.

　　This article mainly introduces the characteristics and applications of ATMEL's CPLD chip ATF1508AS. ATF1508AS is a high-performance, high-density complex programmable logic device (CPLD) implemented using ATMEL's mature electrical erasure technology. It is fully pin-compatible with ALTERA's EPM7000 series; the POF file of EPM7000 can be converted into an industrial industrial file suitable for ATF1508AS. Standard JEDEC programming files are downloaded to the ATF1508AS chip.

1 Features of ATF1508AS

　　ATF1508AS is a high-performance, high-density complex programmable logic device (CPLD) implemented using ATMEL's mature electrical erasure technology. It has 128 logic macro cells and a maximum of 100 inputs, and can easily integrate a range of TTL, SSI, MSI, LSI and traditional PLD logic functions. The enhanced routing switch matrix of the ATF1508AS increases the number of available gates and the success rate of pin lockout when designs are changed, which is very important. ATF1508AS has 96 bidirectional I/O pins and 4 input pins. These 4 input pins can also be used for global control signals, global register clock, global reset and global output enable.

　　Each of the 128 macrocells generates a hidden feedback loop to the global bus, and every input pin and I/O pin also flows into the global bus. Each logic block's switch matrix selects 40 independent signals from the global bus, and each macrocell also generates a return logic entry to the local bus. Cascade logic between macro cells can quickly and efficiently implement complex logic functions. The ATF1508AS includes eight such logic chains, each capable of summing logic terms by fanning in up to 40 product terms.

　　The ATF1508AS is an in-system programming (ISP) device. It uses the industry standard 4-pin JTAG interface (IEEE Standard 1149.1) and is fully compatible with JTAG's Boundary Scan Description Language (BSDL). ISP allows devices to be programmed without removing them from the printed circuit board; in addition to simplifying the production process, ISP also allows design modifications through software.

　　The ATF1508AS's pin hold circuit provides settings for all input and I/O pins. When any pin is driven high or low, and then the pin is left floating, the pin will remain in its previous high or low state. This circuitry prevents unused input and I/O lines from floating to intermediate voltage values, which can cause unnecessary power consumption and system noise. Pin retention circuitry eliminates the need for external pull-up resistors and DC power dissipation.

　　The encryption feature of ATF1508AS can protect the design content of ATF1508AS. The two-byte (16-bit) user signal can be accessed by the user and can store the project name, part number, version or date, etc., and the access of the user signal is not affected by the status of the encryption fuse.

ATF1508AS has a power-on reset feature. During power-up, all I/O pins will be tri-stated until VCC reaches the power-up voltage. This prevents bus contention from occurring during power-up. The registers of ATF1508AS are designed to be reset at power-on. After a small delay from VCC to VRST, all registers will be reset to low level, and the output status should be set according to the polarity of the buffer. This feature is critical for the initialization of state machines.

2 Macrocell of ATF1508AS

　　The macro unit of ATF1508AS is shown in Figure 1. Its macrocells are flexible enough to support highly complex logic functions and operate at high speeds. The macrocell includes five parts: product term and product term selection multiplexer, OR/XOR/cascade logic, flip-flop, output selection and enable, and logic array input. Unused macrounits can be disabled by the compiler to reduce power consumption.

    (1) Product term and product term selection matrix

　　Each macrocell has five product terms, and each product term receives as its input all signals from the global bus and the local bus. The product term selection matrix (PTMUX) allocates these five product terms to the logic gates of the macro unit as needed, and is also responsible for allocating control signals. Programming of the product term selection matrix is ​​determined by the design compiler, which will select the optimized macrocell configuration.

    (2)OR/XOR/cascade logic

　　The logic structure of the ATF1508AS is designed to support all logic efficiently. Within a macrocell, all product terms can be routed into an OR gate, producing a 5-input AND/OR summation term. By fanning in additional product terms through adjacent macrocells, this can be expanded to 40 product terms with only a small delay. The XOR gate of the macrocell allows efficient implementation of comparison and arithmetic functions, where one input of the XOR gate comes from the summation term of the OR operation, and the other input can be a product term or a fixed high or low level. For combinational logic outputs, fixed levels allow polarity selection; for sequential logic, fixed levels allow the use of inversion rules (a corollary of Morgan's law) to simplify the product terms. XOR gates can also be used to simulate T-type and JK-type flip-flops.

    (3) Trigger

　　The ATF1508AS trigger has very flexible data and control functions. The input to the flip-flop can come from an XOR gate, a separate product term, or directly from the I/O port. Selecting individual product terms allows generation of a hidden register feedback within a combinational logic output macrocell (this feature is automatically implemented by the fitter software). In addition to D, T, JK and SR types, the ATF1508AS flip-flop can also be configured as a latch. In this mode, when the clock is high, data passes through; when the clock is low, the data is latched.

The clock signal can be the global CLK signal (GCK) and a separate product term. Flip-flops change state on the rising edge of the clock. When the GCK signal is used as the clock signal, a product term of the macrocell can be selected as the clock enable signal. When using the clock enable function, all clock edges while the enable signal (the product term) is low will be ignored. The flip-flop's asynchronous reset signal (AR) can be a global reset signal (GCLEAR), a product term, or not used. AR can also be the logical OR output of GCLEAR and a product term. The asynchronous assert signal (AP) can be a product term or not used.

    (4) Output selection and enablement

　　ATF1508AS宏单元的输出可以选择为寄存器型和组合型。隐藏的反馈信号可以是组合或寄存器信号而不管输出是组合型还是寄存器型。输出使能多路复用器（MOE）控制输出使能信号。如果是简单的输出操作，任何缓冲器都可以永久使能。如果引脚用作输入，缓冲器也可以永久禁止。在这种配置下，所有的宏单元资源仍然可用，包括隐藏的反馈信号、扩展器和级联逻辑。每一个宏单元的输出使能信号都可以选择一个全局输出使能信号。该器件有6个全局输出使能信号（OE）。

    （5）逻辑阵列输入

　　逻辑阵列输入包括全局总线/开关矩阵和返送总线：

　　◇ 全局总线/开关矩阵

　　全局总线包括所有的输入和I/O引脚信号以及所有128个宏单元的隐藏反馈信号。每个逻辑块的开关矩阵将全局总线的所有信号作为其输入。在软件的控制下，这些信号中最多可以有40个被选择作为逻辑块的输入。

　　◇ 返送总线

　　每一个宏单元可以产生一个返送乘积项。这个信号连接到局部总线上，并且对16个宏单元有效，它是宏单元一个乘积项的反极性。每个局部总线的16个返送项允许产生高扇入求和项（最多21个乘积项），而只有很小的延时。

3 设计软件支持

　　ATMEL公司提供了CPLD的设计软件，而且很多第三方的工具软件也支持ATF1508AS的设计，可以用多种高级描述语言和格式进行逻辑描述，如CUPL、ABEL、VHDL等。由于ATF1508AS与ALTERA公司的EPM7000系列是完全引脚兼容的，因此可以使用ALTERA公司的MAXPLUSII软件。它能进行VHDL语言的编译和综合，使用方便，功能强大。MAXPLUSII综合后产生适合ALTERA的CPLD编程的POF文件，使用POF2JED软件（ATMEL公司提供），就可将POF文件转换为适合ATF1508AS的工业标准JEDEC编程文件，下载到ATF1508AS芯片中。

4 器件编程

　　ATF1508AS器件是利用4脚JTAG协议在系统编程（ISP）的。ATMEL提供了ISP硬件（下载电缆）和软件，以允许从PC对ATF1508AS进行编程。若要允许ISP编程支持"自动测试装置（ATE）"向量，必须通过ATMEL的ISP软件生成串行向量格式（SVF）文件，也可转换为除SVF外的其它ATE测试格式。ATF1508AS器件也可以用标准的第三方编程器来编程，这时JTAG ISP口可以被禁止从而允许这四个额外的I/O引脚用于逻辑功能。

　　ATF1508AS还有一个特性就是如果由于任何原因编程过程被中断，则器件将被锁定以防止输入和I/O引脚被驱动。在这种状态下，输入和I/O引脚缺省下为高阻状态。在编程器件时，输入和I/O引脚也将为高阻状态。此外，引脚保持电路设置在器件编程期间将保持以前的状态。ATF1508AS器件出厂时被初始化为已擦除状态，可以直接用来ISP编程。

5 应用实例

（1）应用ATF1508AS进行串并转换

　　本系统应用ATMEL公司的ATF1508AS进行串行数据到并行数据的转换，在进行数据采集中，用到Crystal半导体公司生产的24位高精度Σ-△模/数转换器CS5321/CS5322组件。该组件最终输出字长为24位的2的补码格式的串行数字信号，将其转换为并行数据可以方便与单片机的接口。串并转换可采用移位寄存器来实现。对实现6通道24位采样，若采用移位寄存器，则需要8位移位寄存器，共3×6=18片，另外还要用几片译码器。这样，会使芯片数量大增，占用大片电路板面积，使系统的体积增大。本系统使用ATF1508AS来实现6通道24位数据的串并转换，可将大部分数字逻辑设计（包括组合逻辑和时序逻辑）集成在一个芯片内，大幅减少芯片数量，减小系统体积。

　　由于ATF1508AS内部有128个宏单元，而且24位串并转换需要24个移位寄存器，因此不能同时进行6通道的串并转换，只能分时复用。本系统分3次进行串并转换，每次转换2个通道，等待单片机读取2个通道的并行数据后再进行剩下的转换。部分串并转换VHDL程序如下（硬件描述语言是VHDL，软件是ALTERA公司的MAXPLUSⅡ软件和ATMEL公司的POF2JED软件，下载软件是ATMEL公司的ATMISP，下载电缆是ATMEL公司的专用电缆）：

s2p : process(SCLK1M,DRDYIN,WORKING,RESET)

begin

if WORKING='1' or RESET='1' then

shift_enable <= '0';

state <= s0;

elsif SCLK1M'event and SCLK1M='0' then

count1 <= count1+1;

case state is

when s0 =>if DRDYIN='0' then

shift_enable <= '1';

count1 <= (others=>'0');

int_reg <= '1';

state <= s1;

elsif READOK='1' then

int_reg <= '1';

end if;

when s1=>shift_reg0<=shift_reg0(22 downto 0)& SOD(0);

shift_reg1<=shift_reg1(22 downto 0)& SOD(1);

if count1=23 then

shift_enable <= '0';

int_reg <= '0';

state <= s2;

else

int_reg <= '1'; end if;

when s2 => if shift_enable='1' then

shift_reg0<=shift_reg0(22 downto 0)& SOD(2);

shift_reg1<=shift_reg1(22 downto 0)& SOD(3);

if count1=23 then

shift_enable <= '0';

int_reg <= '0';

state <= s3;

else

int_reg <= '1'; end if;

elsif READOK='1' then

shift_enable <= '1';

count1 <= (others=>'0');

end if;

when s3 =>if shift_enable='1' then

shift_reg0<=shift_reg0(22 downto 0)& SOD(4);

shift_reg1<=shift_reg1(22 downto 0)& SOD(5);

if count1=23 then

shift_enable <= '0';

int_reg <= '0';

state <= s0;

else

int_reg <= '1'; end if;

elsif READOK='1' then

shift_enable <= '1';

count1 <= (others=>'0');

end if;

end case;

end if;

end process;

（2）应用ATF1508AS进行高速USB通信

　　USB is a new interface technology that has been applied in the PC field in recent years. It has the characteristics of easy use, fast speed, flexible connection, and support for hot swapping. The USB1.1 protocol defines a transmission speed of 12 Mb/s at high speed and 1.5 Mb/s at low speed. To achieve a high-speed speed of 12 Mb/s (equivalent to nearly 1 MB/s), it takes approximately 1 μs to transmit one byte. However, due to the limitations of USB control transmission, error detection and the speed of the microcontroller itself, it is difficult to achieve such a high speed. Therefore, the DMA method must be used to achieve true high-speed transmission. Using CPLD can achieve a similar DMA method. The microcontroller is responsible for interpreting USB control transmission. When data is to be transferred from external storage to the USB interface chip, the microcontroller gives up the bus and the CPLD completes the work. CPLD generates the read timing, address, and chip select signal of the external memory, and at the same time generates the write timing, address, and chip select signal of the USB interface chip. In this way, the work of transferring data from the external memory to the USB interface chip can be automatically realized, and the speed is very fast. No microcontroller intervention is required. The following is a VHDL program fragment of the RAM read timing, address signal and USB interface chip write timing:

rram1: process(SCLK2M) -- RAM_OE (RAM read timing)

begin

if SCLK2M'event and SCLK2M='1' then

if read='0' then

ram_oe_reg <= '1';

cpld2_counter <= (others=>'0');

elsif read='1' then

cpld2_counter <= cpld2_counter+1;

if cpld2_counter>0 then

ram_oe_reg <= not ram_oe_reg;

end if;

end if;

end if;

end process;

rram2: process(SCLK2M,WORKING,RESET) -- ADDRESS (RAM address signal)

begin

if WORKING='1' or RESET='1' then

adr_reg <= (others=>'0');

elsif SCLK2M'event and SCLK2M='0' then

if read='1' and ram_oe_reg='1' and cpld2_counter>2 then

adr_reg <= adr_reg+1;

end if;

end if;

end process;

wd12: process(SCLK2M) --USB chip read timing

begin

if SCLK2M'event and SCLK2M='0' then

if read='0' then

d12_wr_reg <= '1';

elsif read='1' and cpld2_counter/=129 then

d12_wr_reg <= not d12_wr_reg;

end if;

end if;

end process;

Conclusion

The advantages of CPLD devices are shortened development and production cycles, good on-site flexibility, and with the development of electronic technology, their integration level is getting higher and higher, their speed is getting faster, and their prices are gradually decreasing, so the market is developing rapidly. ATMEL's ATF1508AS is a high-performance, high-density complex programmable logic device that is easy to use and highly cost-effective, so it has broad application prospects.