Introduction to the features and applications of AD9833 high-precision programmable waveform generator

AD9833 is a programmable waveform generator that can generate sine wave, triangle wave and square wave output. Waveform generators are widely used in various measurement, excitation and time domain response fields. AD9833 does not require external components. The output frequency and phase can be programmed by software and are easy to adjust. The frequency register is 28 bits. When the main frequency clock is 25MHz, the accuracy is 0.1Hz. When the main frequency clock is 1MHz, the accuracy can reach 0.004Hz.

Data can be written to AD9833 through three serial interfaces. The maximum operating frequency of these three serial ports can reach 40MHz, which is easy to be compatible with DSP and various mainstream microcontrollers. The operating voltage range of AD9833 is 2.3V-5.5V.

AD9833 also has a sleep function, which can make the unused part sleep and reduce the current consumption of this part. For example, if the AD9833 output is used as the clock source, the DAC can be put into sleep to reduce power consumption. The circuit adopts a 10-pin MSOP surface mount package and is very small.

The main features of AD9833 are as follows:

frequency and phase can be digitally programmed;

when the operating voltage is 3V, the power consumption is only 20mW;

the output frequency range is 0MHz-12.5MHz;

the frequency register is 28 bits (with a reference clock of 25MHz, the accuracy is 0.1Hz);

sine wave, triangle wave, and square wave output can be selected;

no external components are required;

3-wire SPI interface;

the temperature range is -40℃-+105℃.

2 Structure and function of AD9833

2.1 Circuit structure

AD9833 is a fully integrated DDS (Direct Digital Frequency Synthesis) circuit that only requires 1 external reference clock, 1 low-precision resistor and a decoupling capacitor to generate a sine wave of up to 12.5MHz. In addition to generating RF signals, the circuit is also widely used in various modulation and demodulation schemes. These schemes are all used in the digital field. The use of DSP technology can simplify complex modulation and demodulation algorithms and is very accurate.

The internal circuit of AD9833 mainly includes numerically controlled oscillator (NCO), frequency and phase regulator, Sine ROM, digital-to-analog converter (DAC), and voltage regulator. Its functional block diagram is shown in Figure 1.



The core of AD933 is a 28-bit phase accumulator, which consists of an adder and a phase register. The phase register increases in steps for each clock. The output of the phase register is added to the phase control word and input into the address of the sine lookup table. The sine lookup table contains the digital amplitude information of a sine wave cycle, and each address corresponds to a phase point in the range of 0°-360° in the sine wave. The lookup table maps the input address phase information into a digital signal of the sine wave amplitude, and outputs the analog quantity to the DAC. The phase register returns to the initial state after every 228/M MCLK clocks, and the sine lookup table returns to the initial position after a cycle, thus outputting a sine wave. The output sine wave frequency is:

fOUT = M (fMCLK/228) (1)

Where M is the frequency control word, which is given by external programming and has a range of 0 ≤ M ≤ 228-1.

The VDD pin is used to power the analog and digital parts of AD9833, and the power supply voltage is 2.3V-5.5V. The internal digital circuit operating voltage of AD9833 is 2.5V, and the voltage regulator on the board can generate a 2.5V stable voltage from VDD. Note: If VDD is less than or equal to 2.7V, the pin CAP/2.5V should be directly connected to VDD.

2.2 Functional Description

AD9833 has 3 serial interface lines, which are compatible with SPI, QSPI, MI-CROWIRE and DSP interface standards. Under the action of the serial port clock SCLK, data is loaded into the device in 16-bit mode. The timing diagram is shown in Figure 3. The FSYNC pin is an enable pin, level-triggered, and low level is valid. When performing serial data transmission, the FSYNC pin must be set low, and attention should be paid to the minimum value of the setup time t7 from the effective FSYNC to the falling edge of SCLK. After FSYNC is set low, the data is sent to the input shift register of AD9833 at the falling edge of 16 SCLKs. FSYNC can be set high at the falling edge of the 16th SCLK, but attention should be paid to the minimum and maximum values ​​of the data holding time ts from the falling edge of SCLK to the rising edge of FSYNC. Of course, it is also possible to continuously load multiple 16-bit data when FSYNC is low, and set FSYNC high only at the falling edge of the 16th SCLK of the last data. Finally, it should be noted that the SCLK clock is a high-low level pulse when writing data, but when FSYNC just starts to become low (when writing data is about to start), SCLK must be high (note the parameter t11).

When the AD9833 is initialized, in order to avoid false output of the DAC, RESET must be set to 1 (RESET will not reset the frequency, phase and control registers). RESET will not be set to 0 until the configuration is completed and the output is required; the waveform can be observed at the output of the DAC 8-9 MCLK clock cycles after RESET is 0.

There is a certain response time in between when the AD9833 writes data to the output end to get a response. Each time new data is loaded to the frequency or phase register, there will be a delay of 7-8 MCLK clock cycles before the waveform at the output end changes. There is an uncertainty of 1 MCLK clock cycle because the rising edge position of MCLK is uncertain when the data is loaded into the destination register.

3 Pin Function and Timing of AD9833

The pin arrangement of AD9833 is shown in Figure 2, and the function description of each pin is shown in Table 1.





The timing characteristics of AD9833 are shown in Figure 3, Figure 4 and Table 2.