Dynamic Management of Energy Consumption in Embedded Systems

Historically, low power consumption in embedded processors was achieved by using some low-power idle or sleep modes. Today, embedded processors are tasked with more complex tasks that require higher performance. New applications (such as audio and video playback and games) generally run for a long time, and the ratio of "running time" to "idle time" is rising rapidly. Traditional power management techniques are very effective during idle time, but they are powerless to save battery energy during operation.

In addition, power management chip manufacturers have focused only on the management of power supply. Generally, embedded processor suppliers provide input/output power requirements, and power semiconductor suppliers compete to develop ICs that meet the requirements as efficiently as possible. However, power management IC efficiencies such as switching regulators have now reached a peak of 95%. This forces today's power IC suppliers to compete not only on price, but also on every tiny increase in efficiency. Current trends in the mobile phone market show that these traditional methods can no longer meet the industry's demand for improved efficiency.

Despite steady improvements in battery technology, such as longer life and smaller size, this progress has not kept pace with the rapidly increasing power requirements of next-generation designs. Conventional power management methods are no longer sufficient to extend battery life in new products to levels acceptable to end users.
Trends in process technology have also increased the complexity of power management. In the past, CMOS transistors consumed little or no power when static. However, as speed and density increase, process geometries continue to shrink and static power consumption increases. It is estimated that for chips implemented in a high-speed 0.13 micron process, static power consumption accounts for 15-20% of total power consumption. Moreover, as process technology moves below 100 nanometers, static power consumption will increase exponentially and will become a major component of total processor power consumption.

One way to reconcile the contradiction between high performance and low power consumption is to let the processor run at different performance levels according to the current workload. For example, an MPEG video player requires an order of magnitude higher processing performance than an MP3 audio player. Therefore, when playing MP3, the processor can run at a lower frequency while still ensuring high quality playback. When the clock frequency is reduced, the processor's power supply voltage can be reduced at the same time to achieve energy saving.

Dynamic voltage scaling (DVS) takes advantage of the fact that the peak frequency of a CMOS-process processor is proportional to the supply voltage. Figure 1 shows the frequency vs. voltage relationship, using an ARM926EJ-S processor core (0.18 micron process) for testing. It can be seen that the turning point is around 90 MHz, which is at the limit of the voltage range where the scaling technique is applicable.

The following is an approximate power equation for a CMOS circuit:

P = CVDD 2fc + VDDIQ
Where:
P is the power consumed by the supply voltage VDD
C(VDD)2fc is the dynamic power consumption due to switching (C is the capacitance, fc is the frequency)
VDDIQ is the static power consumption due to leakage (IQ is the leakage current)

Obviously, for a given load, the amount of dynamic power is proportional to the square of the supply voltage.

By reducing the supply voltage and simultaneously reducing the processor clock speed, power consumption will decrease quadratically at the expense of increased run time. Since the amount of energy stored in a battery after each charge is limited, energy management techniques are the only way to extend battery life. Figure 2 shows the equivalent energy savings when both frequency and voltage are reduced from their maximum values. Because the voltage cannot be reduced beyond a certain minimum, reducing the frequency below the curve will not produce any additional energy savings. Therefore, there is a frequency range in which energy management techniques are effective (about 90-170 MHz in this case).

Requirements for voltage control and frequency control

Figure 3 compares the effects of two power management methods, one using dynamic voltage scaling (DVS) and the other a conventional gating power management method. The DVS method can significantly reduce the overall power consumption.

In general, processors run too fast. For example, from a QoS perspective, if the software only needs to display 30 frames of video in one second, it doesn't make sense for the processor to complete all decoding in half a second. Doing tasks early makes less efficient use of energy.

The key to achieving a balance between performance and power efficiency is to use intelligent software that can reduce processor performance to the level that just meets the bottom line of application software requirements. This software should include "performance setting" algorithms that determine the optimal performance level at which the processor should run and manage performance adjustment technologies such as DVS.

Advanced voltage control requirements

Existing DVS systems use open-loop control techniques where the CPU's characteristics are determined by the workload at a given clock speed and voltage, with enough margin to accommodate variations in temperature, power supply, and wafer process.

Embedded processors are designed to operate over a wide temperature range and to accommodate different silicon processes. Therefore, a higher safety margin must be used to ensure adequate safe operating range when power efficiency decreases. As the supply voltage moves toward 1.2V or lower, the percentage of safety margin required also increases to cover the various variations in temperature and silicon process.

CMOS circuits slow down as temperature increases, an effect that must be factored into the supply voltage safety margin, even though normal operating temperature is room temperature. Due to the many variables in process technology, such as differences between different cores, different wafers, different batches, and even different foundries, these guard-bands can be quite wide to ensure high yields, which has a significant impact on overall power consumption.

A frequency vs. voltage table can be constructed using a large number of features to ensure that performance requirements are met under all operating conditions. A certain voltage/speed combination is then hard-coded into the chip. In practice, a custom software driver on the SoC sets the required voltage level through a dedicated hardware interface. Before changing the clock frequency, a stable voltage state (VDD_OK) must be checked by a timer or other method.

The adaptive voltage scaling (AVS) method is a closed-loop control technique that is a significant improvement over DVS. AVS uses inherent compensation for process and temperature variations, simplifies the voltage adjustment method, and no longer requires a frequency/voltage table. The implementation of this technology requires the use of several hardware performance monitors in conjunction with the embedded processor, which receive requests to change performance levels from the performance setting algorithm. These performance monitors can accurately monitor process and temperature variations inside and outside the core, and communicate with the external energy management unit (EMU) through a standard interface.

ARM-National Semiconductor Energy Management Solutions

ARM has been working on a solution that provides intelligent control of performance tuning hardware. National Semiconductor has been working on a solution that provides intelligent control of supply voltage, simplifies DVS methods, and reduces safety margins through AVS. The two companies can now provide an end-to-end solution to developers of battery-powered devices.

ARM's Intelligent Energy Manager (IEM) solution is centered around a software component, the Intelligent Energy Management software. The IEM software interfaces with the operating system (OS) running under the application software, using parameters obtained from the internal architecture of the OS to "guide" the use of the OS through the running applications. Some complex software algorithms can be used to evaluate different types of software activities and then generate a prediction of future performance. Each prediction result is summed up using a measurement stack to determine an overall performance prediction.

The working of the policy stack is shown in Figure 4. Each algorithm sends its prediction into the stack as a performance level (PeRF.), and each prediction has an associated instruction indicating the weight of the current prediction. If the confidence level is low, IGNORE (abandon the prediction), if it is high, SET (specify the prediction), SET_IFGT means that if the confidence level of the prediction is the highest in the stack, then this level should be used. When a special event occurs in the system, such as a task switch, the different predictions are re-evaluated from the bottom of the stack upwards to derive a unique overall performance prediction.

Working in conjunction with the IEM software is the Intelligent Energy Controller (IEC) component. The IEC is an APB peripheral that can be quickly integrated into any SoC design based on the AMBA specification. The IEC uses precision counters and timers to measure the current system performance level and sends it to the software to ensure that the processor's performance always meets the minimum requirements of the software workload. It also offloads most of the software measurement activities to the hardware, thereby reducing the overhead of the IEM software on the processor.

The IEC component also provides an abstraction for the performance tuning hardware. From the software's perspective, a new performance level request is submitted to the IEC when the workload changes and the prediction is modified. The implementation of this performance level is hidden from the software in an abstract way. Similarly, the performance setting algorithm of ARM's IEM software component to optimize power consumption is based on workload differences. Similarly, National Semiconductor's PowerWise technology also ensures that the processor does not operate in the worst case by adjusting operating parameters according to the current environmental conditions and process differences between devices.

The core of National Semiconductor's PowerWise technology for adaptive voltage scaling or dynamic voltage scaling is a low-gate-count, integrated digital component called the Adaptive Power Controller (APC). The APC includes a hardware performance monitor that can accurately monitor processor power consumption and track temperature and variations in different device processes. The APC communicates with the off-chip energy management unit (EMU) through a two-wire, bidirectional bus called the PowerWise Interface (PWI).

Figure 5 shows the complete end-to-end reference solution, which uses the IEM and IEC components from ARM, and the APC and EMU components from National Semiconductor.

The overall performance level predicted by ARM's IEM is passed to APC through the abstraction layer of the IEM hardware part. APC adaptively adjusts the supply voltage to cover the core process and the current operating conditions to meet the specific performance requirements.

During design, the IEC can be configured to connect to the specially designed clock management unit (CMU) and APC components on the chip. The CMU is responsible for providing the processor with a clock frequency that is appropriate for the required performance level. The APC is responsible for managing the off-chip EMU to provide the processor core with the minimum voltage that can meet the required performance level, while also taking into account the current core process and temperature conditions. The IEC component coordinates and manages the changes in clock frequency and voltage to ensure that the combination of the two is valid at any time, and the transition between different performance levels is smooth and as fast as possible within the constraints of the clock generation scheme and the external EMU.

Maximum energy management

ARM and National Semiconductor have developed these advanced energy management solutions to help OEMs maximize the battery life of their handheld battery-powered products (battery life is now one of the few key factors that end users really care about). The componentized nature of the entire solution means that the technology can self-adjust to various performance adjustment hardware, including DVS and AVS. The IEM prediction software determines the minimum performance level at which the processor can run, and through the help of the IEC, it also ensures that it never falls below the minimum software limit. The APC works with the external EMU using performance prediction to run the processor at the lowest voltage and frequency that ensures that the application software can run correctly. This complete solution can minimize the power consumption of the processor within the constraints of the determined clock generator, the dynamic range of the supply voltage, and the available headroom for the mixed application software.

ARM intelligent energy management technology can be used to reduce the energy requirements of an embedded processor by up to 75%. National Semiconductor's PowerWise technology can reduce the safety margin and further reduce energy consumption. Compared with the open-loop voltage control solution, the use of AVS at room temperature can save another 45% of energy consumption. Simulation work and test chips show that the combination of IEM and PowerWise technology can reduce the total energy consumption of products such as smartphones and PDAs by 30%, which is of great benefit to increasing battery life, while also reducing product size or reducing costs.

As mentioned earlier, in a typical design, the processor is just one of many power-consuming components. When IEM and PowerWise technologies become available, it is expected that they will be used in an SoC to control other devices.