IBIS Models: Using IBIS Models to Study Signal Integrity Issues

This article is about using digital input/output buffer information specification (IBIS) simulation models during the printed circuit board (PCB) development phase. This article will describe how to use an IBIS model to extract some important variables for signal integrity calculations and determine PCB design solutions. Note that this extracted value is an integral part of the IBIS model.

Figure 1 Mismatched termination impedance PCB device

Signal Integrity Issues
When looking at digital signals at both ends of a transmission line, designers are often surprised by what happens when the signal is driven into a PCB trace. Over relatively long distances, electrical signals behave more like traveling waves than instantaneous signals. A good analog to describe the behavior of electrical waves on a circuit board is a wave in a pool. Ripple waves travel smoothly through a pool because two equal volumes of water have the same "impedance." However, the impedance of the pool walls differ significantly and reflect the wave in the opposite direction. The same phenomenon occurs with electrical signals injected into a PCB trace, which reflect in a similar manner when there is an impedance mismatch. Figure 1 shows a PCB setup with mismatched termination impedances. A microcontroller, a TI MSP430™, sends a clock signal to a TI ADS8326 ADC, which sends converted data back to the MSP430. Figure 2 shows the reflections created by the impedance mismatch in this setup. These reflections cause signal integrity issues on the transmission trace. Matching the electrical impedance of the PCB traces at one or both ends can greatly reduce reflections.

Figure 2: Mismatched termination impedance in Figure 1 causes reflection

To solve the problem of system electrical impedance matching, designers need to understand the impedance characteristics of the integrated circuit (IC) and the impedance characteristics of the PCB traces that act as transmission traces. Knowing these characteristics allows designers to model each connection element as a distributed transmission trace.

Transmission traces serve a variety of circuits, from single-ended and differential-ended devices to open-drain output devices. This article focuses on single-ended transmission traces whose drivers have a push-pull output circuit design. Figure 3 shows the components used to design this example transmission trace.

Figure 3 Example single-ended transmission line circuit

In addition, the following IC pin specifications are required:
 Transmitter output resistance ZT (Ω)
 Transmitter rise time tRise and fall time tFall (seconds)
 Receiver input resistance ZR (Ω)
 Receiver pin capacitance CR_Pin (F)

These specifications are not usually found in the IC manufacturer's datasheet. As this article will show, all of these values ​​can be obtained from the IC's IBIS model during the process of designing the PCB and using the model to simulate the PCB transmission traces.

A transmission trace is defined using the following parameters:
Characteristic impedance Z0 (Ω)
Propagation delay D (ps/inch)
Trace propagation delay tD (ps)
Trace length LENGTH (inch)

Depending on the specific PCB design, this list of variables can be longer. For example, a PCB design may have a base plate with multiple transmission/receiver points. 3 All transmission trace values ​​are specific to the specific PCB. In general, Z0 for FR-4 boards ranges from 50 to 75Ω, while D ranges from 140 to 180 ps/inch. The actual values ​​of Z0 and D depend on the material and physical dimensions of the actual transmission trace. 4 The trace propagation delay for a specific board can be calculated as:

tD=D × LENGTH。(1)

For an FR-4 board, a reasonable propagation delay for the trace (see Figure 4) is 178 ps/inch, and the characteristic impedance is 50Ω. This can be verified on the board by measuring the wire inductance and capacitance of the trace and plugging these values ​​into the following equations:
(2)
or
(3)
and
(4)

CTR is the trace conductor capacitance in farads/inch; LTR is the trace conductor inductance in hens/inch; 85 ps/inch is the air dielectric constant; and er is the material dielectric constant. For example, if the microstrip-board conductor capacitance is 2.6 pF/inch, the conductor inductance is 6.4 nH/inch, and D=129 ps/inch, Z0=49.4Ω.

Figure 4 Cross-section of microstrip board and stripline board

Lumped vs. Distributed Circuits
Once the transmission line is defined, the next step is to determine whether the circuit layout represents a lumped system or a distributed system. Generally speaking, lumped systems are smaller, while distributed circuits require more board space. Small circuits have an effective length (LENGTH) that is smaller than the fastest electrical characteristics in terms of signals. To qualify as a lumped system, the circuit on the PCB must meet the following requirements:
(5)
Where tRise is the rise time in seconds.

Once a lumped circuit is implemented on a PCB, termination strategy is not an issue. Fundamentally, we assume that the driver signal delivered into the transmission line reaches the receiver instantaneously.

Data Organization of IBIS Models
An IBIS model includes data for three, six, or nine corners, depending on the supply voltage range of the IC. The variables that determine these corners are the silicon process1, supply voltage, and junction temperature. The specific process/voltage/temperature (PVT) SPICE corners for a device model are critical to creating an accurate IBIS model. Different silicon processes with different ratings create weaker or stronger models. The designer defines the voltage setting based on the power requirements of the component and varies it between the rated value, minimum, and maximum values. Finally, the temperature setting of the component silicon junction is determined based on the component's specified temperature range, rated power dissipation, and the package's junction-to-ambient thermal resistance, or θJA.

Table 1 lists an example of three PVT variables and their relationship to the CMOS process for TI's 24-bit biopotential measurement ADC ADS129x family. These variables are used to perform six SPICE simulations. The first and fourth simulations both use the nominal process model, nominal supply voltage, and junction temperature at room temperature. The second and fifth simulations both use a weak process model, low supply voltage, and high junction temperature. The third and sixth simulations use a strong process model, higher supply voltage, and lower junction temperature. The relationship between the PVT values ​​maps the optimal corners of the CMOS process.

Table 1 PVT simulation angle of ADS1296 IBIS model

Number of corners	Silicon Process	Supply voltage ( V )	Temperature ( °C )
1	Rated	1.8	27
2	weak	1.65	85
3	powerful	2.0	-40
4	Rated	3.3	27
5	weak	3.0	85
6	powerful	3.6	-40

Finding and/or Calculating Transmitter Specifications
Required transmitter specifications for signal integrity assessment include output impedance (ZT) and rise and fall times (tRise and tFall, respectively). Figure 5 shows the TI ADS1296 package listed from the IBIS model file ads129x.ibs. 5The values ​​used to generate the impedance are shown under the “[Pin]” keyword, which is also in the buffer model (not shown). The rise and fall times are located in the transient section of the IBIS model data listing.

Figure 5 IBIS model package list for ADS1296, including L_pin and C_pin values

Impedance of Input and Output Pins
The pin impedance of any signal is composed of the package inductance and capacitance added to the model impedance. In Figure 5, the keywords “[Component]”, “[Manufacturer]”, and “[Package]” describe a specific package, the 64-pin PBGA (ZXG). The package inductance and capacitance of a specific pin can be found under the “[Pin]” keyword. For example, at pin 5E, signal GPIO4, the L_pin and C_pin values ​​can be found. The L_pin (pin inductance) and C_pin (pin capacitance) values ​​for this signal and package are 1.4891 nH and 0.28001 pF.
The second important capacitance value is the silicon capacitor, C_comp. The C_comp value can be found under the “[Model]” keyword in the model DIO_33 listing in the ads129x.ibs file (see Figure 6). C_comp in this model is the capacitance of the DIO buffer, which has a power pin voltage of 3.3V. The "|" symbol indicates a comment; therefore, the valid C_comp values ​​in this list are 3.0727220e-12 F (typical), 2.3187130e-12 F (minimum), and 3.8529520e-12 F (maximum) from which the PCB designer can select. The 3.072722 pF typical value is the correct choice during the PCB transmission line design phase.

Figure 6 ads129x.ibs file C_comp value model DIO_33 list

Figure 7 Termination-Correction Strategy

Input and output impedances are critical to signal transmission. The following equations define the characteristic impedance of the IBIS model pin:
(6)
Output rise and fall times
Throughout the industry, the convention for rise and fall time specifications is to use the time required for the output signal to swing between 10% and 90% of the rail-to-rail signal, which is generally 0 to DVDD. The IBIS Open Forum has the same definition for rise time, which was adopted due to the longer tail of the CMOS switching waveform.

The output, I/O, and tri-state models within the IBIS model have some specifications located under the “[Ramp]” keyword for R_load (test load), dV/dt_r (rise time), and dV/dt_f (fall time). The rise and fall time data ranges from 20% to 80% of the voltage-output signal. If the denominator of the typical dV/dt_r value is multiplied by 0.8/0.6, the rise time value will change from a 20%-80% swing to a 10%-90% swing. Note that this data represents a buffer with a resistive load (R_load). The DIO_33 data in the ads129x.ibs file assumes a 50-Ω load, so the data does not reach DVDD. The values ​​produced by this calculation provide the correct tRise values ​​for various transmission line calculations, such as fKnee, f3dB, and rise length.

Designing Transmission Lines Using IBIS
This article starts with a discussion of a PCB with mismatched termination impedance. After that, we use the IBIS model to understand and find some key components of this transmission problem. At this point, there should be a solution to this problem. Figure 7 shows the termination correction strategy, and Figure 8 shows the waveform after correction.

Figure 8: Stable signal after termination correction

If you want to design a PCB transmission line, the first step is to collect information from the product manual. The second step is to check the IBIS model to find some parameters that cannot be obtained from the manual - input/output impedance, rise time and input/output capacitance. When entering the hardware stage, you need to use the IBIS model to find some key product specifications and simulate the final design.