Simulation of the world: parallel current sharing characteristics of SiC MOSFET single tube

Preface

Infineon has released a lot of technical information on the parallel connection of SiC MOSFET to help you better understand and apply it. This article will use the device SPICE model and Simetrix simulation environment to analyze the current sharing characteristics of SiC MOSFET single tubes under parallel conditions.

special reminder

Simulation cannot replace experiments and is for reference only.

1. Select simulation research object

SiC MOSFET

IMZ120R045M1 (1200V/45mΩ), TO247-4pin, two in parallel

Driver IC

1EDI40I12AF, single channel, magnetic isolation, drive current ±4A (min)

2. Simulation circuit Setup

As shown in Figure 1, based on the idea of ​​dual pulses, a main circuit and a drive circuit with dual tubes in parallel are built, and relevant stray parameters are set. The ambient temperature is room temperature.

External main circuit: DC source 800Vdc, bus capacitor (including parasitic parameters), stray inductance Ldc_P and Ldc_N between bus capacitor and half-bridge circuit, double pulse inductor Ls_DPT

Parallel main circuit: The overall structure is a half-bridge structure, with dual pulses driving the lower bridge SiC MOSFET to commutate with the upper bridge SiC MOSFET Body Diode. The lower bridge is two IMZ120R045M1 Q11 and Q12, which are connected in parallel through their respective emitter (source) inductors Lex_Q11 and Lex_Q12, and their respective collector (drain) inductors Lcx_Q11 and Lcx_Q12; similarly, the parallel structure of Q21 and Q22 of the upper bridge is also connected in a similar way.

Parallel drive circuit: Based on the TO247-4pin Kelvin structure, the power emitter and the signal emitter stage can be decoupled from each other. In addition, the 1EDI40I12AF driver chip is equipped with OUTP and OUTN pins, so the driving part of each single tube has its own Rgon, Rgoff and Rgee (emitter resistance), which are connected in parallel to the corresponding pins on the secondary side of the driver IC.

Driver part settings: By adjusting the secondary power supply and voltage regulator circuit of the driver IC, adjust the gate voltage Vgs=+15V/-3V, and then set the gate resistance Rgon=15Ω, Rgoff=5Ω, Rgee is first approximately set to 0Ω (1pΩ), plus the PCB trace inductance between the single tube gate and the driver IC.

Figure 1. Schematic diagram of a dual pulse circuit based on TO247-4Pin SiC dual tube parallel connection

3. Parallel dynamic current sharing simulation

The dynamic current sharing of SiC MOSFET in parallel is similar to that of IGBT, except that SiC MOSFET has a faster switching speed and is more sensitive to some parallel parameters. As shown in Figure 2, we first analyze the dynamic current sharing characteristics of lower bridge Q11 and Q12 during double pulse switching and its influencing factors:

Figure 2. Schematic diagram of the double pulse circuit with two lower bridge SiC tubes in parallel

3.1 Effect of device external power source inductance Lex on parallel switch characteristics

Set Lex_Q11=5nH, Lex_Q12=10nH, other parameters and simulation results are as follows:

Figure 3. Parallel current sharing simulation results of different Lex inductors

3.2 Effect of device external power drain inductance Lcx on parallel switch characteristics

Set Lcx_Q11=5nH, Lcx_Q12=10nH, other parameters and simulation results are as follows:

Figure 4. Parallel current sharing simulation results of different Lcx inductors

3.3 Effect of device external gate-level inductance Lgx on parallel switch characteristics

Set the gate-level inductance Lgx_Q11=20nH, Lgx_Q12=40nH, where the gate-level inductance of Rgon and Rgoff is Lgx. Other parameters and simulation results are as follows:

Figure 5. Parallel current sharing simulation results of different Lgx inductors

3.4 Effect of device external source loop inductance Lgxe and loop resistance Rgee on parallel switch characteristics

In the case of asymmetric Lex inductance (unbalanced current), set different source suppression inductors and resistors

Lgxe=20nH, Rgee=1Ω and 3Ω, to see the suppression and current sharing effect on the driving circulation, the simulation results are as follows:

Figure 6. Changes in current sharing characteristics before (dashed line) and after (solid line) adding source suppression inductors and resistors

Figure 7. Current sharing characteristics for different source suppression inductors and resistors (1Ω dashed line) and (3Ω solid line)

4. Summary

Based on the simulation conditions and results of two parallel-connected TO247-4pin SiC MOSFETs, we can draw the following preliminary conclusions:

1. The source inductance Lex of the parallel single tube is different. The current sharing of the SiC MOSFET when it is turned on and off is very sensitive to this. Because the difference in source inductance will also couple to the drive circuit, further affecting the current sharing. As shown in Figure 8 below, taking the shutdown as an example, due to the difference in source inductance Lex, the source circulating current and the potential difference of the source (VQ11_EE-VQ12_EE) are caused, which pushes up the source voltage VQ11_EE of Q11, and indirectly reduces the voltage Vgs_Q11 between the gate and the source of Q11.

Figure 8. Source circulating current and source potential difference at turn-off for different source inductances

2. The difference in drain inductance Lcx of parallel single tubes has a significantly lower impact on current sharing than the source inductance, because the drain inductance will not directly affect the source current loop formed by the auxiliary source and the power source.

3. The difference in gate inductance has little effect on dynamic current sharing, and the driving voltage Vgs waveform has almost no change. If the total stray inductance of the main circuit is reduced and the gate resistance is reduced, so that SiC works in a faster di/dt and dv/dt environment, the effect of gate inductance on current sharing may be slightly more obvious.

4. The auxiliary source resistor Rgee is not very effective in suppressing source circulating current and improving dynamic current sharing.

Here is another question: since Rgee has a general effect on suppressing source loop current, what if we add a little Cge capacitance to the gate? Please see the following simulation:

Figure 9 Effect of adding 1nF gate-level Cge capacitance on source current inequality characteristics (dashed line means no Cge, solid line means with Cge)

It can be seen from the above simulation that the Cge capacitor has almost no effect on shutdown, and Cge only increases Eon at a slower turn-on speed and reduces turn-on current oscillation, but has little effect on the current sharing difference and loss difference during turn-on.