Engineers' practical experience: A "unique" approach to PSR primary-side feedback switching power supply design

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  Currently, the more popular low-cost, ultra-small space-consuming design solutions basically adopt the PSR primary-side feedback flyback type. The primary-side feedback voltage regulation eliminates the voltage feedback loop (TL431 and optocoupler) and the lower EMC radiation eliminates the Y capacitor, which not only saves cost but also space, and is adopted by many power engineers.

  Next, I will talk about my "unique" method of designing PSR primary-side feedback switching power supplies based on actual practice - based on actual practice.

  Requirements:

  Full voltage input, output 5V/1A, in line with Energy Star 2 standards, IEC60950 and EN55022 safety and EMC standards. Because chargers are usually small in size for portability, 5W switching power chargers usually use smaller EFD-15 and EPC13 transformers. According to conventional calculations, such transformers may be considered too small to be CORE. If someone still thinks so, you are OUT.

  The magnetic core is determined. The following will talk about the design of 5V/1A5W power transformer using EFD15 and EPC13 transformers respectively.

  1.EFD15 transformer design

  Currently, for small transformer cores, especially small companies, they have basically no way of knowing the B/H curve of the CORE, because the PSR circuit has certain requirements on the transformer leakage inductance.

  So start with designing the transformer to minimize leakage inductance:

  It is known that the output current is 1A and the power of 5W is relatively small, so the current density of the copper wire is selected as 8A/mm2.

  The diameter of the secondary copper wire is: SQRT(1/8/3.14)*2=0.4mm.

  By measuring or checking the BOBBIN data, we can know that the width of the BOBBIN of EFD15 is 9.2mm.

  Since the secondary uses triple insulated wire, the actual diameter of the 0.4mm triple insulated wire is 0.6mm.

  In order to reduce the leakage inductance, the secondary coil is designed as a whole layer. The secondary impurities are: 9.2/0.6mm=15.3Ts, take 15Ts.

  Since the IC generally has a built-in MOS with a VDS withstand voltage of 600~650V, a stress voltage margin of 50~100V is required to be kept considering the leakage inductance spike, so the reflected voltage needs to be controlled within 100V.

  So: (Vout+VF)*n<100, that is: n<100/(5+1), n<16.6,

  Take n=16.5, and get the primary turns NP=15*16.5=247.5

  Take NP=248, substitute it into the above formula to verify, (Vout+VF)*(NP/NS)<100,

  That is, (5+1)*(248/15)=99.2<100, established.

  Determine NP=248Ts.

  Assumption: The primary 248Ts is wound in three layers on BOBBIN. Due to the multi-layer winding, considering the gap between the wires and the unevenness above the second layer, at least 1Ts margin (gap) must be left.

  It is found that the available outer diameter of the primary copper wire is: 9.2/(248/3+1)=0.109mm, and the corresponding actual copper wire diameter is 0.089mm, which is too small (less than 0.1mm is difficult to wind) and is not advisable.

  Assumption: The primary 248Ts is wound in 4 layers on BOBBIN, the available outer diameter of the primary copper wire is: 9.2/(248/4+1)=0.146mm, the corresponding copper wire diameter is 0.126mm, and the actual available copper wire diameter is 0.12mm.

  The lower limit of IC's VCC voltage is generally 10~12V. Considering that at least 3V margin is left, the VCC voltage is about 15V.

  So: NV=Vnv/(Vout+VF)*NS=15/(5+1)*15=37.5Ts, take 38Ts.

  Because PSR uses NV coils for voltage stabilization, the leakage inductance of NV also needs to be controlled, and the design is still based on the entire layer.

  The NV wire diameter is 9.2/(38+1)=0.235mm, and the corresponding copper wire diameter is 0.215mm. The actual copper wire diameter can be 0.2mm. You can also use 0.1mm double wires.

  At this point, the number of turns of each coil is determined.

  After wrapping the shield, keep the TAPE1 layer;

  Wind the primary again, in 4 layers according to the above calculation, and wrap it with 1 layer of TAPE after completion;

  In order to reduce the influence of the distributed capacitance between the primary and secondary on EMC, a shield is wound with a 0.1mm wire and wrapped with a TAPE1 layer;

  Then wrap the secondary and wrap it with TAPE1 layer;

  Then wrap the feedback and wrap it with TAPE2 layer. Some people may ask: Why didn’t you calculate the inductance? As mentioned before, the B/H of CORE is uncertain, so we must first determine the saturated AL value.

  Grind the center column of the transformer CORE a little, then install the coil wound in the above way, and use an oscilloscope to detect the waveform on Rsenes, see R5 in the figure below.

Engineers' practical experience: A

  Input AC90V/50Hz, slowly load, and observe whether the CORE is saturated. If there are signs of saturation, remove it and grind it again... until the load reaches 1.1~1.2A and there is just a little sign of saturation. (This waveform needs to be enlarged to full screen for best observation)

  OK, remove the transformer and measure the inductance. The measured inductance is used as the maximum value, and an error range and margin of +3%~+5% is appropriately reserved based on the manufacturer's manufacturing capabilities. For example, if the measured inductance is 2mH, then 2-2*0.05=1.9mH is taken, and the error is +/-0.1mH.

  Now let's verify the winding space of the transformer BOBBIN with the above parameters.

  It is known that the diameter of the copper wires E1 and E2 is 0.1mm, and the actual outer diameter is 0.12mm;

  The diameter of NP copper wire is 0.12mm, and the actual outer diameter is 0.14mm;

  The diameter of NS copper wire is 0.4mm, and the actual outer diameter is 0.6mm;

  TAPE uses 0.025mm thick Mylar tape.

  A.

  If the copper wire diameter of NV is 0.2mm, the actual outer diameter is 0.22mm

  The thickness of one side of the wire package is: E1+TAPE+NP+TAPE+E2+TAPE+NS+TAPE+NV+TAPE

  =0.12+0.025+0.14*4+0.025+0.12+0.025+0.6+0.025+0.22+0.025*2=1.77mm.

  B.

  If NV uses a copper wire with a diameter of 0.1mm and double wires, the actual outer diameter is 0.12mm

  The thickness of one side of the wire package is: E1+TAPE+NP+TAPE+E2+TAPE+NS+TAPE+NV+TAPE

  =0.12+0.025+0.14*4+0.025+0.12+0.025+0.6+0.025+0.12+0.025*2=1.67mm.

  The single-side slot depth of EFD15 BOBBIN is 2.0mm, so both winding methods are feasible.

  2. Transformer design of EPC13

  Still using the above design method, measuring or checking the BOBBIN data, we can find that the width of EPC13BOBBIN is 6.8mm.

  The secondary turns are: 6.8/0.6=11.3Ts, take 11Ts.

  The number of primary turns is: 11*16.5=181.5Ts, take 182Ts.

  The number of feedback turns is: 15/(5+1)*11=27.5Ts, take 28Ts.

  The winding method of EPC13 is the same as that of EFD15, so it will not be repeated here.

  The above transformer design differences are based on the control of leakage inductance. All parameters (Schottky VF, MOS voltage stress margin, etc.) are zero boundaries or limits. In actual design, the secondary winding will be reduced by 1~2 turns due to the crossing of the same-name end of the secondary winding corresponding to the output PIN position, or the output flying lead sleeve Teflon sleeve, or the supplier's process capability. The corresponding primary and feedback turns also need to be reduced according to the turns ratio. In addition, the current market competition has led manufacturers to reduce the VDS withstand voltage of the IC built-in MOS tube to save costs. In order to retain a larger voltage stress margin, the primary turns need to be reduced again. The above modifications will have a negative impact on EMC radiation, and the corresponding trade-offs need to be weighed, but the premise is that the product must work in DCM mode.

  I have been using the PSR primary feedback solution to design products since it was launched in 2008. Looking back, there are many different brands of PSR solutions on the market. Compared with the newly launched PSR control ICs, some have been continuously improved due to poor market response, while others have been cost-reduced due to vicious competition. I will mainly talk about the cost-reduced parts.

  Due to the patent restrictions of some brands on IC packaging technology, most of the ICs with built-in MOS (not only PSR control ICs, but also PWM control ICs) currently use the method of placing the control wafer and MOS wafer on the substrate and connecting them with gold wires as jumpers. This leads to two problematic products:

  1. EMC radiation caused by gold wire.

  2. The company that develops control wafers can control the cost of control wafers by itself, but MOS wafers are generally purchased from MOS wafer manufacturers. In this way, the cost control of MOS wafers also becomes a major issue in IC cost control.

  Radiation can be controlled using optimized design.

  However, the path to COSTDOWN of MOS wafers comes from reducing the withstand voltage of its VDS. Currently, many ICs of different brands have reduced the built-in MOS with a VDS of 650V to 620~630V, or even 560~600V. In this way, it is not enough to only control the leakage inductance to reduce the VDS peak voltage, so a larger voltage stress margin must be reserved for VDS.

  Next, we will take EPC13 as an example to explain the transformer design after optimization.

  The method is the same as above. First calculate the secondary. Considering that the output flying lead is covered with Teflon sleeve or the output line crosses the BOBBINPIN position, it is necessary to reserve 1 turn of space. The number of secondary turns is: 6.8/0.6-1=10.3, and 10Ts is taken.

  Then calculate the primary turns. Considering the larger voltage stress margin for the MOS tube, the reflected voltage is taken as 75% of the previous value.

  So: (Vout+VF)*n<100*75%

  To output 5V/1A, a 2A/40V Schottky can be used. The VF value of a 2A/40V Schottky is generally 0.55V.

  Substituting into the above formula, we get: n<13.51,

  Take 13.5, and we get NP=10*13.5=135Ts.

  Substituting into the above formula, we can verify that (5+0.55)*(135/10)=74.925<75, which is true.

  Determine NP=135Ts.

  Next, calculate the number of feedback turns:

  The feedback voltage is still 15V.

  So, 15/(5+0.55)*10=27Ts.

  Next, determine the winding order.

  Because it works in DCM mode and adopts Y-free design, DI/DT is relatively large. The air gap of transformer core grinding will produce strong penetrating stray magnetic flux, which will cause eddy current in coil test and affect EMC noise. Therefore, it is necessary to first wrap a layer of 0.1mm diameter copper wire on BOBBIN as a shield, and lead out the ground wire terminated by NV.

Reference address:Engineers' practical experience: A "unique" approach to PSR primary-side feedback switching power supply design

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