Low dropout (LDO) regulator to ADC power supply interface

 Considering the sampling speeds of currently available ADCs and the many different voltage and clock domains inside a typical ADC, it is generally recommended to separate the different power supply inputs. By having the different power supply inputs belong to different domains, crosstalk between the supplies can be minimized, and it will be more difficult for noise to cross the different domains to avoid creeping and causing ADC performance issues. If it is not possible to put them on different domains, at least use components such as ferrite beads to provide some isolation between the different power domains. One way to drive the different power supply inputs separately is to use low dropout (LDO) regulators. An example is shown in Figure 1 below.

Figure 1

figure 1

Use different LDOs to drive different ADC supplies

LDOs are generally the safest type of power supply with the least risk for driving the ADC supply input. In general, LDOs have very low noise and a high power supply rejection ratio (PSRR). Low dropout voltage generally means that the input supply to the LDO can be as low as only a few hundred millivolts above the output voltage of the LDO. For example, the ADP1741 2A LDO has as little as 400 mV of headroom (Vin must be 400 mV above Vout). For a typical ADC’s ​​1.8 V rail, this means the LDO’s efficiency is about Vout/Vin = 1.8/2.2 = 81.8%.

This is not inefficient in any sense, but you will find that more efficient devices can be used to drive the ADC supply input. However, these devices do not achieve their high efficiency in a vacuum. As mentioned earlier, the two main advantages of LDOs are low noise and high PSRR. Other devices often trade noise for efficiency.

For the ADP1741, the output noise is typically 65 µVrms from 10 Hz to 100 kHz for an output voltage of 2.5 V. Here is an example to illustrate the impact of this noise contribution. A 14-bit, 250 MSPS ADC has a full-scale input of 2.0 Vpp, an SNR of 70 dB, and a noise floor of 20 nVrms/rt-Hz. In the first Nyquist zone, the ADC noise will be 223.61 µVrms (20 nVrms/rt-Hz * sqrt(250 MHz/2)). In this case, the ADP1741 output noise is much lower than the ADC noise. In addition, the ADC's PSRR (typically 60 dB) further reduces the ADP1741 noise from 65 µVrms to 65 nVrms (65 µVrms X 1 mV/V). It is easy to see why an LDO is an excellent choice for driving the supply input. It has almost no effect on the ADC noise.

However, this comes at a cost. An obvious disadvantage of using an LDO is its potential power dissipation. For example, assume that the 14-bit ADC in the previous example is a four-channel device with a total power dissipation of 2 W, of which 1 W is required for the AVDD supply. In this case, the input supply to the LDO is limited, and we only have a 6 V input available to drive the 1.8 V AVDD supply. This means that the ADP1741 will need to dissipate approximately (6 V – 1.8 V)/1800 mA = 2.33 W of power. The maximum junction temperature (Tj) of the ADP1741 will be pushed up to TA + Pd X Θja = 85°C + (2.33 WX 42°C/W) = 183°C, exceeding the 150°C maximum rating of the LDO.

This is, of course, an extreme example, but it illustrates the importance of needing to provide a low input voltage to the LDO. This can result in the need to use multiple LDOs to step down the voltage from the higher input supply rail to the lower input supply rail required by the ADC.