High-speed and high-precision motion controller using DSP+FPGADSP+FPGA

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High-speed and high-precision motion controller using DSP+FPGADSP+FPGA [Copy link]

Digital signal processors have efficient numerical computing capabilities and can provide a good development environment, while programmable logic devices have highly flexible configurability. This article describes the use of TMS320C32 floating-point DSP and programmable logic devices (FPGA) to form a high-speed, high-precision motion controller. The system uses the B-spline interpolation algorithm to smooth the motion curve and uses the discrete PID algorithm to control the motion process.

Motion control cards have been widely used in CNC machine tools, industrial robots, medical equipment, plotters, IC circuit manufacturing equipment, IC packaging and other fields, and have achieved good results. At present, most motion control cards use 8051 series 8-bit microcontrollers, which save development cycles but lack flexibility, are not competent for high-demand operating environments, and have limited computing power.

DSP has powerful data processing functions. Even in very complex control, the sampling period can be very small, and the control effect is closer to that of a continuous system. Combining the respective advantages of DSP and PC will be the development trend of high-performance CNC systems. This motion controller uses TI's high-performance floating-point DSP as the main control chip, coordinates and exchanges data with the PC through the ISA interface, uses the PC computer as the basic platform, and uses the DSP high-speed motion control card as the core of fine interpolation and servo control to control the motion of the linear motor, achieving good practical application results.

1. The main hardware components of high-speed and high-precision motion control card

The task of this motion control system is to control the motion of the linear motor, which requires 4-axis input and 4-axis output, uses a grating ruler to count the input, and has a 16-bit parallel high-speed DA output. The motion positioning accuracy is required to reach 10nm and the response time is <100ns.

The high-speed linear motor is the control object of this system. It has the characteristics of fast acceleration (a>10g) and high movement speed (v>300mm/s). The control system is required to have a sufficiently short response time (<100ns) and a sufficiently high positioning accuracy (10nm level), so the processing power and computing power of the core CPU of the system must meet the high-speed requirements; in addition, the core of the linear motor motion positioning is a high-precision feedback control device. The feedback control device of the linear motor is a grating ruler and a high-precision pulse counter. The grating ruler sends a number of pulses that is linearly related to the movement distance. The count value of the pulse counter represents the current movement position of the linear motor. After calculation, a counter with a counting length of 28 bits can meet the positioning accuracy requirements, and the counting frequency is very high. The general general counter parameters cannot be achieved, so it is necessary to design a special counter. In order to facilitate the setting of the motion parameters of the target point and enable the motion control card to have a better human-computer interaction function, the system must have the function of communicating with the PC.

Taking the above requirements into consideration, the system is designed in the form of DSP+FPGA, with the DSP main control chip as the central processing module, the FPGA as the feedback counting module and responsible for part of the logic decoding work on the board, the PC communication interface module uses a dual-port RAM, and the output module is implemented with a D/A converter, as shown in Figure 1.

1.1 DSP module

The motion control system based on DSP generally uses TI's TMS320C24x series chips, but the 24x series is a 16-bit fixed-point processor with limited computing power. It cannot meet the high-speed and high-precision requirements of this system planning. Therefore, we selected TI's TMS320C32 DSP as the main control chip.

The TMS320C3X series chip is the first generation of floating-point DSP chips launched by TI in the United States. It has a rich instruction set, high computing speed, large address space and high cost performance, and has been widely used in various fields. TMS320C32 is a new product of the TMS320 series floating-point digital signal processor. It is simplified and improved on the basis of TMS320C30 and TMS320C31. The structural improvements mainly include variable-width memory interface, faster instruction cycle time, dual-channel DMA processor with settable priority, flexible boot program loading mode, relocatable interrupt vector table and optional edge/level triggered interrupt mode.

The development of TMS320C32 can be done in assembly language or C language. The advantage of using assembly language is that it runs fast and can make full use of the hardware characteristics of the chip, but the development speed is slow and the program readability is poor; the advantage of C language is that it is easy to program, debug quickly, and has good readability, which can greatly shorten the development cycle, but C language cannot operate on the special function registers that do not have mapped addresses in the chip, such as IF and IE, AR0~AR7, etc.

1.2 FPGA module

The main function of this part is a 4-channel pulse counter for the grating ruler. In addition, it also undertakes part of the address decoding work. However, due to the high pulse counting frequency and large number of counts, a high-capacity and high-performance programmable logic device must be selected.

ALTERA FLEX (Flexibl Logic Element Matrix) 10K series FPGA, ranging from 10,000 gates to 100,000 gates, can provide 720 to 5392 triggers and 6144 to 24576 bits of RAM, and provide several speed levels such as 30ns, 40ns and 50ns, which can adapt to the signal processing rate of 18 to 105MHz. ALTERA FLEX10K series FPGA is mainly composed of input and output units IOE, buried array EAB, logic array LAB and internal connections. EAB is a RAM block with registers added to the input and output ports, and its capacity can be flexibly changed. Therefore, EAB can not only be used for memory, but also can be used to form circuits such as multipliers and error correction logic by writing table values in advance. When used for RAM, EAB can be configured into various forms of word width and capacity.

LAB is mainly used for logic circuit design. A LAB includes 8 logic units LE. Each LAB provides 4 control signals and their inverted signals, two of which can be used for clock signals. Each LE includes combinational logic and a programmable trigger. The trigger can be configured in various forms such as D, T, JK, RS, etc. IOE provides global clock and clear signal input ports, as well as various programmable input and output ports, such as low-noise ports, high-speed ports, etc.

FLEX10K series chips are PLD products recently launched by ALTERA. Compared with the MAX7000 series EPLD previously launched by ALTERA, the FLEX10K (hereinafter referred to as 10K) series has richer internal resources (up to 100,000 gates) and more configurable I/O pins (up to 406). Coupled with its low price, the 10K series chips are becoming more and more popular among users.

Based on the above reasons, we use ALTERA FLEX10K10 in this solution, and considering the continuity of future designs, we can replace it with ALTERA FLEX 10K20 with higher performance, the same size and the same pin configuration without changing the hardware circuit.

1.3 PC Communication Interface Module

The module uses a 16-bit ISA bus to connect to the PC, and a CY7C133 dual-port RAM is used as data buffer.

Because the ISA bus is very flexible and convenient to use, and the I/O operation is relatively simple. Although the ISA bus has many pins, not all of them are used. The key is the application of several fixed pins, such as I/O CH RDY, I/OR, I/OW, ALE, data line and address line, which are combined to achieve communication.

In this system, the PC-side address line of the dual-port RAM does not directly use the address line from ISA, but is given by the address counter inside the FPGA. This is because most of the addresses on the ISA bus have been allocated by the PC system, and it is not realistic to directly map the 2K dual-port RAM data space to the ISA bus; and the data exchanged between the control system and the PC is basically a series of coordinate parameters of processing points, and sequential access has no effect on performance. Therefore, sequential access using the address counter method can fully meet the design requirements.

The specific method is: A2~A9 of the ISA address line is connected to the address comparator 74LS688, which is compared with the set address. The chip select signal of 74LS688 is provided by the "AND" of IOR and IOW of ISA (IOR and IOW are low effective when the ISA bus accesses the port), and A0 and A1 are connected to FPGA to select 4 registers with different functions inside the FPGA. ALE of ISA is used to trigger the internal logic function of FPGA and latch the signal from the ISA bus.

When accessing the address clear register, the address count value is cleared; when accessing the address increment register, the address count value is increased by "1". And so on, accessing different registers will perform different operations on the address count value, and the address count value is directly sent to the dual-port RAM as the address, so that the ISA bus can access the dual-port RAM.

1.4 Output Module

The output module adopts analog output and drives the motor through external amplification. The D/A conversion chip is DAC7744.

DAC7744 is a high-performance 4-channel 16-bit high-speed D/A with the following main features:

Output channel: 4 independent channels

Output signal range: 0～5V; 0～10V*; ±5V; ±10V

Output impedance: ≤2Ω

D/A converter device: DAC7744

D/A conversion resolution: 16 bits

D/A conversion code: binary original code (unipolar) binary offset code (bipolar)

D/A conversion time: ≤1uS

D/A conversion comprehensive error: ≤0.02﹪ FSR

Voltage output mode load capacity: 5mA/each channel

1.5 Storage Module

The storage module is used to store system programs and data, and is mainly composed of SRAM (2 CY7C1021) and FLASH (AM29F400B). The peripheral storage circuit is shown in Figure 3:

2. Software Design

The motion control card is inserted into the ISA slot of the industrial computer and works with the host computer. First, the processing curve is input into the host NC machine, and the host computer performs rough interpolation, and then transmits the data to the control card through the ISA interface. The control card performs fine interpolation on the received data - using cubic B-spline interpolation, and then sends it to the DA to drive the motor to move. The DSP counts pulses through the FPGA, reads the feedback information of the linear motor grating ruler, and then uses the discrete PID control algorithm to adjust it to optimize the motor motion control.

The core of the motion control algorithm is to first use the B-spline interpolation method to further refine the target point to make the motion curve smoother, and then use the PID algorithm to make adjustments during the motion process, ultimately achieving the design requirements of high speed and high precision.

2.1 B-spline interpolation

At present, many advanced CAD/CAM systems have adopted B-spline curves. Its characteristics are that it can accurately represent analytical curves (such as straight lines, conic curves, etc.) and free curves (such as uniform B-spline curves, etc.) in a unified mathematical form, so it is easy to manage and store with a unified database, and the amount of programs can be greatly reduced; the weight factor in the definition of non-uniform B-spline curves makes the shape design more flexible and convenient, and designers can achieve the desired effect by adjusting the points, lines, and surface elements with intuitive geometric meanings.

This system uses cubic B-spline curve as the fine interpolation algorithm, which can achieve satisfactory results when applied to the control card. Only the position data of 4 adjacent points are needed in the calculation process to construct a smooth curve. The formula is expressed in the form of coordinate components:

2.2 PID control

In the field of control, PID control algorithm is a commonly used algorithm. PID is the abbreviation of proportional, integral and differential. Reasonable parameter estimation and comparison of PID can be obtained through MATLAB transfer function model simulation.

Since the system is a digital system and uses digital quantities, the PID algorithm must be discretized before it can be used. Since the system's storage space is limited, the algorithm's storage space overhead cannot be too large, so a discretized incremental PID algorithm is used. During the calculation process, the algorithm only needs to retain the error data of the last three times to deduce the next output, saving a lot of data space, improving the calculation speed, and has strong practical value. The formula is as follows:

μ(k) and μ(k-1) are the output at time k and k-1 respectively, which are reflected as the output of DA in the system.

e(k), e(k-1), and e(k-2) are the deviation values at moments k, k-1, and k-2, respectively, which are reflected in the system as the deviation between the actual position and the target position at that moment.

It is a constant in the PID formula. Different values represent the strength and effect of the differential, integral and proportional regulation of the PID system.

3. Summary

In the open CNC system, the motion control card based on DSP+FPGA is applied. DSP assumes the module function with high real-time requirements in the CNC system. By utilizing the high-speed computing power and real-time signal processing capability of DSP and adopting the advanced Bspline interpolation algorithm, the DSP motion control card has high-speed and high-precision performance. Combined with the advanced technology of FPGA chip, the integration and reliability of the motion control card are greatly improved. This motion control card is currently designed based on the ISA bus. In the future, we will consider transplanting the system to the PCI bus, which will further improve the system's processing speed and adapt to higher requirements.

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