Overall Design of New LCD Driver Circuit IP Core

　　This article introduces the design of the general driver circuit IP core for LCD. It uses a top-down design method to divide it into several main modules, introduces the functions of each module, describes it in VHDL language, implements it with FPGA and passes simulation verification. This IP core has good portability and can drive LCD circuits of different sizes.

　　introduction

　　LCD has emerged as a new force in display technology due to its advantages such as low operating voltage, low power consumption, large amount of displayed information, long life, easy integration, convenient carrying and low electromagnetic radiation pollution. It is widely used in portable electronic products and equipment such as mobile phones, PDA products, and handheld instruments.

　　LCD driver circuit is an important part of liquid crystal display system. It is an interface circuit between computer (or MCU) and liquid crystal screen. Its main function is to establish AC driving electric field by modulating the phase, peak value, frequency and other parameters of the potential signal output to the electrode of liquid crystal display device. Due to the large difference in LCD specifications, the conventional method is to develop a dedicated driver circuit for each LCD. Such a design wastes time and has poor reusability. Therefore, it is very necessary to design an IP core that can be used for most small-scale LCD driver circuits and solve this problem by reusing the IP core. At present, only Yu-Jung Huang et al. of I-Shou University have designed a driver circuit IP core that can drive LCDs of different sizes. This function is achieved by implanting an embedded microprocessor in the system. However, this embedded microprocessor makes the system more complex and more expensive. The driver circuit IP core designed in this paper that can drive LCDs of different sizes is implemented by FPGA, which can effectively overcome the two shortcomings of complex circuit system and high cost.

　　Design Specifications

　　In order to meet the actual needs of most of today's smaller-scale LCD display applications, the LCD driver circuit IP core chip designed in this article has 64 COM (rows) and 64 SEG (columns) outputs, a high-speed 8-bit parallel MCU interface and a serial interface. The chip contains RAM for storing display data, and 10 control terminals are specially designed for convenient and flexible control. It has the following main functions:

　　1. Provide scanning timing signals and display signal data for the LCD display;

　　2. Support direct connection with MCU in bus form;

　　3. It can drive LCDs of different sizes (n×m), n can take continuous values ​​(n=0~63), and m can only take multiples of 8 (m=8k, k takes a natural number);

　　4. Support cascading between IP cores to drive larger LCDs, supporting up to 4 IP cores for row-to-row cascading and column-to-column cascading;

　　5. Can provide a wider driving output voltage range to adapt to different LCD devices;

　　6. Provide functions such as picture-in-picture and split-screen display.

　　IP core design

　　This paper follows the "top-down" design method. First, the chip is divided into hierarchical functions. At the same time, it refers to the existing design experience of LCD driver chips and combines the "bottom-up" design method to design some modules. Finally, the modules are coordinated according to the system design framework, and the overall function of the chip is verified, thus meeting the requirements of the design specifications.

　　system structure

　　The IP core system structure designed in this paper is shown in Figure 1. The IP core is mainly composed of the following modules: row scanning and column signal driving module, level converter, preset ring counter, data latch module, control logic module, display data RAM and address decoding module, MCU interface module. Some of the large modules can be subdivided into several submodules.

　　Figure 1 IP core system structure

　　Design of each module

　　MCU Interface Module

　　The MCU interface module is the interface for the IP core to communicate with the external controller (MCU), and is the channel for data transmission. The MCU uses this interface to write commands to the LCD driver chip, read status or display data. At the same time, the interface is also controlled by the command decoder, so that reading and writing are combined with internal operations. The chip is implemented by a relatively complex internal combinational logic and sequential logic circuit, which is compatible with the two current mainstream MCU control signals and supports serial/parallel data operation modes.

　　In addition to several submodules commonly used in the MCU interface module of the existing common LCD driver circuit, such as the data bus (8-bit) submodule, the busy state detection submodule, the read-write control submodule, and the MCU release submodule, this module has newly added a row cascade and column cascade control submodule. The data bus is mainly used for internal and external data exchange; the busy state detection submodule is used to determine the MCU state, generate a system busy flag signal to coordinate the signal read and write operations and receive internal/external reset signals; the read-write control submodule is used to generate the correct read-write control timing; the function of the MCU release submodule is to release the MCU through logical combination when the chip executes the "read-modify-write" process, so that the MCU can perform other operations at the same time; and the main function of the newly added cascade control submodule is to realize row cascade and column cascade between IP cores, which can support up to 16 IP cascades (4 levels for rows and columns). CS0~CS1 is the row cascade control terminal, and CS2~CS3 is the column cascade control terminal. For example, suppose there is an LCD (128×256) that can be driven by 8 IP cores. When setting, set CS to 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111 respectively, and a 2×4 driving IP core array can be formed. The arrangement diagram is shown in Figure 2.

　　Figure 2 IP core cascade arrangement diagram (24)

　　Display data RAM and address decoding module

　　This module is mainly used to store the data to be displayed, and acts as a buffer between the MCU interface and the signal driving circuit to ensure the stable output of the display data.

　　The module includes two submodules: a RAM array for storing display data and an address decoder. First, the column address circuit provides the column address, and the column address decoder selects a column of 8-bit RAM storage units, which the MCU reads/writes through the interface; then, the row address decoder scans the RAM in units of rows, and combined with the display data latch circuit, the output of the entire row of data can be realized, and output to the liquid crystal display through the electrode drive circuit for display.

　　Data latch module

　　This module contains two submodules: column number control latch submodule and drive latch submodule. The column number control latch submodule is composed of k parallel 8-bit data latches. Its main function is to latch the data on the data bus. Under the control signal and clock signal of the control logic module, the display data signal output from the RAM to the 8-bit data bus is latched in the corresponding 8-bit data latch. 64-bit data needs 8 times, 8 bits are input each time. The drive latch submodule is a 64-bit drive latch composed of 64 1-bit latches in parallel. Its function is to latch all the m-bit data transmitted from the above 8 8-bit data latches at once under the control signal and clock signal of the control logic module, and then input it to the column signal electrode drive module behind.

　　Control Logic Module

　　The main function of this module is to control signal data transmission and select the number of column signal lines. The column number control latch submodule, drive latch submodule and clock generator can be controlled through the column number control input terminal M to realize functions suitable for LCDs of different sizes. According to needs, by inputting different values ​​to the column number control input terminal M, it is possible to control how many column number control latches are in working state, and the other latch units are set to idle state. During the working cycle, the data in the display data RAM is latched into the corresponding column number control latch through the 8-bit data bus, and then latched into the drive latch again under the control of a clock signal as the input signal of the electrode drive module. In this way, the IP core can realize the function of controlling the selection of the number of drive columns. When M is "000", the lower 8 bits (the first latch) of the column number control latch work, and the others are all idle, and the corresponding column electrodes are SEG0~SEG7; when M is "001", the lower 16 bits (the first and second latches) of the column number control latch work, and the others are all idle, and the corresponding column electrodes are SEG0~SEG15; and so on, until all 64-bit registers of the column number control latch work, and the corresponding column electrodes are SEG0~SEG63.

　　Electrode drive module

　　The module mainly contains four submodules: a row scanning electrode driving submodule, a column signal electrode driving submodule, a level converter and a presettable ring counter.

　　The function of the level converter is to convert the voltage of the logic signal into the actual LCD driving voltage through the external control signal according to the needs of the actual application, and output it to the driving module; the function of the row scanning electrode driving submodule is to provide a certain period of scanning signal pulses to the row electrode; the function of the column signal electrode driving submodule is to apply the data from the latch to the corresponding column electrode, and establish an AC driving electric field with the scanning signal of the row electrode, thereby driving the display of the LCD device. The presettable ring counter can control the number of row scanning electrodes through the row number control terminal N (S0~S5) to adapt to LCD screens of different sizes. According to actual needs, different values ​​are input to the row number control terminal N to control the number of specific working rows, and all other electrodes are idle. Under the control of the row driving clock signal, scan row by row, repeating repeatedly until a new value is input to the row number control terminal N, and then scan row by row on the new number of row electrodes. For example, when the external signal N is "011011", the number of scanning electrodes is 27, and the row scanning driving submodule generates a row-by-row scanning signal on the row electrodes COM0~COM26, and the other row electrodes COM27~COM63 are all set to a low level, and the cycle repeats. If a new external signal N is applied as "100011", the scanning electrode driving submodule generates a cyclic row-by-row scanning signal on the row electrodes COM0~COM34.

　　IP core system implementation

　　First, according to the above definition and division of the whole system function and the design of each module, each functional module is modeled with VHDL language; secondly, on Xilinx's FPGA device, the EDA tool ISE is used to simulate and debug, and optimize the design; then, the top-level module is defined with VHDL to connect the modules, and the corresponding system debugging and verification are carried out; finally, an LCD driving circuit is obtained, which has 64 COM (rows) and 64 SEG (columns) outputs, a high-speed 8-bit parallel MCU interface and a serial interface, a RAM for storing display data, and can be cascaded and expanded through the cascade control terminal CS to meet the needs of larger LCDs, and can adapt to LCDs of different sizes through the column number control terminal M and the row number control terminal N.

　　Simulation and Verification

　　This paper uses Xilinx's simulation software ISE as a simulation tool and verifies the designed IP core in two steps.

　　First, this paper conducts a preliminary functional verification of each module (including internal submodules) of the IP core. Then, referring to the working process of the chip, the entire chip is simulated as a whole. Figures 3 and 4 are the simulation results obtained by simulating the row and column control functions of the entire IP core using ISE. In the figure, CLK and CLK1 are the data transmission control clock and row electrode scanning pulse of the MCU interface module respectively; M and N are the column electrode and row electrode number selection control terminals respectively; the lower two bits and upper two bits of CS are the row cascade and column cascade control terminals respectively.

　　Figure 3 Simulation results of row control function

　　Figure 4 Column control function simulation results

　　The simulation results of Figures 3 and 4 illustrate:

　　1. When RESET is high, the IP core is in the initial state or cleared state; when WRITE is high, the IP core is in the working state and can receive display data.

　　2. At the rising edge of the clock CLK, the MCU writes 8-bit display data in parallel to the RAM of the IP core through the interface; at the rising edge of the clock CLK1, the row scan drive electrodes output scan pulses in sequence, and the column signal electrodes output the data in the RAM from the SEG.

　　3. The row number control terminal can change the number of electrodes for row scanning. When the row number selection control terminal N is "3E", the scanning signal is output on COM0~COM61. As shown in Figure 3, at the first row clock signal, the scanning signal is output on the electrode COM61, and under the control of the row drive clock, the row electrodes are scanned row by row; at the seventh row clock signal, N becomes "22", and the scanning signal becomes output on the row electrode COM33, and COM0~COM33 are scanned row by row.

　　4. The column number control terminal can change the number of electrodes of the column signal. When the column number selection control terminal M is "110", the SEG electrode has a 48-bit output; when M is "010", the SEG output becomes 16 bits; when M is "101", the SEG output becomes 40 bits; when M is "100", the SEG output becomes 32 bits.

　　This article has verified the functions of the IP core, including column control, row control, and inter-core cascading, and all of them have passed the verification. Due to space limitations, only the column and row control functions are introduced here.

　　Conclusion

　　This paper discusses the design of an IP core for LCD display driver chip. Based on the top-down design concept, the chip is divided into hierarchical functions and the overall function of the chip is verified. In the functional verification of the chip, this paper uses the VHDL hardware description language to simulate and verify the logic function and timing relationship of the circuit. Due to the use of parameterized design, the LCD display driver has good portability and can be easily applied to various scales of flat panel display system applications in portable instruments, PDAs and other related products.