Application of digital comparator and analog-to-digital converter of digital power controller UCD3138

　　The digital power controller UCD3138 has 4 integrated digital comparators, and its input and reference values ​​can be flexibly configured. The absolute value of the analog front end (AFE) module and the output of the EADC can be used as the input of the digital comparator, so the use of digital comparators can achieve fault response and protection of the system output voltage. UCD3138 has 16 integrated analog-to-digital converters (ADCs), of which the analog-to-digital converter named ADC15 is not open to the outside and can be used to detect the EAP or EAN pins of any of the 3 AFE modules to achieve accurate acquisition of the system output voltage, and ultimately achieve fault response and protection of the output voltage.

　　1. UCD3138 digital comparator

　　UCD3138 has 4 digital comparators integrated inside, which can use the absolute value or error value of AFE as input, flexibly configure reference value, and finally achieve fast response and protection to system output voltage faults (overvoltage, undervoltage, etc.).

　　1.1 Introduction to the hardware circuit of the digital comparator

　　Figure 1 shows the block diagram of the analog front end (AFE) inside the UCD3138 chip. After voltage division, the output voltage enters the AFE module in the form of a differential signal, and is compared with the reference voltage (the output value of DAC0) to obtain an error signal (analog quantity); the error signal is converted into a digital quantity after analog-to-digital conversion, and then input into the digital loop compensation module (Filter).

　　Figure 1. UCD3138 AFE Module Block Diagram

　　To enrich the flexibility of the application, the reference value (digital quantity) set by the user is added to the output value (digital quantity) of the EADC to generate a digital signal called "absolute value", which can represent the actual collected voltage information (ie, the value of Vd).

　　The digital comparator of UCD3138 takes the digital error signal (value at point B) or the absolute value (value at point C) as one input terminal and the reference voltage value (which can be set by the user) as another input terminal. After being triggered, it can be configured to shut down any DPWM.

　　There are 3 AFE modules in UCD3138, and similarly, there are 4 digital comparators.

　　1.2 Key registers involved in digital comparator

　　1.2.1 EADC Output

　　The output of EADC is the information of the value after the reference voltage is subtracted from the input analog value after digitization, that is, the digital error amount, and its range is directly related to the gain of the AFE itself. For example, when the gain value is set to 1, the output range is +248~-256; and when the gain is set to 8, the output range is +31~-32.

　　The 0th to 8th bits (9 bits in total, named RAW_ERROR_VALUE) of the register EADCRAWVALUE store the output of EADC, with a resolution of 1mV/bit.

　　1.2.2 DAC Input

　　The output of DAC is the reference voltage of the system. In the actual application of UCD3138, the user can set the input value of DAC as a digital signal. The 4th to 13th bits (10 bits in total, named DAC_VALUE) of the register EADCDAC save the user's setting value. The resolution is 1.5625mV/bit.

　　1.2.3 Absolute value

　　The 16th to 25th bits (10 bits in total, named ABS_VALUE) of the register EADCVALUE store the absolute value with a resolution of 1.5625mV/bit.

　　As mentioned above, the absolute value is obtained by adding the output information of the EADC and the input information of the DAC, but it is not a direct addition of the two digital quantities because their resolutions are different. In fact, the analog quantities represented by the above three digital quantities are in an equation relationship.

　　For example, under certain conditions, the output of the EADC (ERROR_VALUE) is 192; the input of the DAC is 747; and the absolute value (ABS_VALUE) is 624, as shown in Figure 2 below.

　　Figure 2. Register values ​​read from the Memory Debugger

　　Obviously, 747-624=123≠192. However, the respective analog quantities satisfy the equation as follows:

　　► The analog value corresponding to the output 192 of EADC is 192×1mV/bit=192mV;

　　► The analog value corresponding to the DAC input 747 is 747×1.5625mV/bit=1167.1875mV;

　　► The analog value corresponding to the absolute value 624 is 624×1.5625mV/bit=975mV;

　　◎ Finally, 1167.1875-975=192.1875≈ 192.

　　Alternatively, the three digital quantities can have the following equation relationship after adding the attenuation coefficient:

　　1.3 Software Configuration of Digital Comparator

　　In the initialization phase of the program, the configuration of the digital comparator can be completed. Taking the configuration of digital comparator 0 as an example, the main code is as follows:

　　FaultMuxRegs.DCOMPCTRL0.bit.CNT_THRESH = 1;

　　The above code configuration only needs to trigger the digital comparator once to generate a fault.

　　FaultMuxRegs.DCOMPCTRL0.bit.FE_SEL = 0;

　　The above code configures the input of the digital comparator to be the absolute value of AFE0. It can also be configured as the output of EADC. In addition, the absolute values ​​of the other two AFEs and the output of EADC can also be configured as the input of digital comparator 0.

　　FaultMuxRegs.DCOMPCTRL0.bit.COMP_POL = 1;

　　The above code is configured so that the digital comparator will not trigger until the input is higher than the reference value.

　　FaultMuxRegs.DCOMPCTRL0.bit.THRESH = 850;

　　The reference value is set to 850. If the input value is selected as an absolute value, the digital comparator will be triggered when the Vd voltage is greater than 850×1.5625mV/bit =1.33V.

　　FaultMuxRegs.DPWM0FLTABDET.bit.DCOMP0_EN=1;

　　The above code is configured to shut down DPWM0A and DPWM0B immediately after the digital comparator is triggered.

　　1.4 Practical Application Results of Digital Comparator

　　During actual debugging, an adjustable voltage is connected to Vd in Figure 1 and slowly increases from 0V. It can be observed that when the voltage exceeds 1.33V, the drive signal is immediately turned off, which is in line with expectations, as shown in Figure 3 below (CH3 is Vd voltage, CH2 is DPWM0B).

　　Figure 3. Turning off DPWM0B after the digital comparator is triggered

　　1.5 Practical Application Results of Digital Comparator

　　In practical applications, attention should be paid to the saturation problem of EADC.

　　As mentioned in Section 1.2 above, the output of the EADC has a certain range. When the input is too large or too small, the output of the EADC will be fixed at its upper or lower limit, and the EADC is in saturation at this time. The above-mentioned experiment is still used as the background for explanation, in which the gain of the AFE is set to 1.

　　When the Vd voltage is 554mV, the absolute value is expected to be 355 (because 554/1.5625≈355), and the EADC output is expected to be 613 (refer to the last equation in Section 1.2). However, the actual reading shows that the absolute value is 588 and the EADC output is 248, which is completely different from the assumption. Analysis of the reason shows that the EADC is already in positive saturation at this time, and the upper limit of the output is 248.

　　Figure 4. EADC Forward Saturation

　　Similarly, when the Vd voltage is 1.64V, the absolute value is expected to be 1050 (because 1640/1.5625≈1050), and the EADC output is expected to be -473 (refer to the last equation in Section 1.2). However, the actual reading shows that the absolute value is 911 and the EADC output is -256, which is completely different from the assumption. The reason for this is that the EADC is already in negative saturation at this time, and the lower limit of the output is -256.

　　Figure 5. EADC Negative Saturation

　　From the above analysis, we can see that after the DAC value is fixed, the absolute value has a range, which is directly related to the gain of the AFE, as shown in the following table.

　　Table 1. Relationship between absolute value range and AFE gain

　　AFE GainDAC ValueEADC ValueAbsolute Value

　　1x+248 to -256(x-159) to (x+164)

　　2x+124 to -128(x-79) to (x+82)

　　4x+62 to -64(x-40) to (x+41)

　　8x+31 to -32(x-20) to (x+20)

　　It can be observed that if the gain of the AFE is set to 8 and the DAC value is 747, the absolute value range is 727~767. At this point, if the digital comparator is planned to be triggered when Vd is 1.33V, its reference value needs to be set to 850. However, the other end of the digital comparator (input is the absolute value) is only 767 at most, so the digital comparator will not have a chance to be triggered.

　　In practical applications, the gain of the AFE needs to be considered when setting the reference value of the digital comparator to prevent the output of the EADC from being clamped and failing to trigger the digital comparator due to premature saturation of the EADC.

　　2. UCD3138's internal analog-to-digital converter ADC15

　　There are 16 analog-to-digital converters in the UCD3138 chip, of which ADC15 can be connected to the EAP or EAN pin of the AFE module inside the chip. In practical applications, ADC15 can be used to detect the feedback voltage of the system and restore the actual output voltage in the software.

　　2.1 ADC15 Configuration

　　The ADC15 inside the UCD3138 chip can be connected to the EAP or EAN pin of any AFE module to complete the digitization of the analog signal. When applied, it is very similar to the configuration method of other ADCs. The only difference is that ADC15 needs to be configured to the specified AFE.

　　The following three lines of code complete the association between ADC15 and AFE. Among them, AFE_MUX_CH_SEL is 1, which means ADC15 is connected to AFE0; AFE_VIN_MUX is 0, which means ADC15 is connected to the EAP pin.

　　MiscAnalogRegs.AFECTRL.bit.AFE_MUX_SEL=3;

　　MiscAnalogRegs.AFECTRL.bit.AFE_VIN_MUX=0;

　　MiscAnalogRegs.AFECTRL.bit.AFE_MUX_CH_SEL=1;

　　Based on the above configuration, ADC15 is connected to the EAP pin of AFE0, which can detect the Vd voltage in Figure 1.

　　2.2 Experimental Results

　　As shown in Figure 4, when Vd is 554mV, the result of ADC15 (adc_values.Vout) is 902. The two are approximately consistent with the following equation:

　　As shown in Figure 5, when Vd is 1.64V, the result of ADC15 (adc_values.Vout) is 2681. The two are approximately consistent with the following equation:

　　The difference between the above physical values ​​and digital quantities is mainly caused by measurement errors.

　　3. UCD3138's internal analog-to-digital converter ADC15

　　The digital comparator and analog-to-digital converter ADC15 inside the UCD3138 chip can be used to handle work related to the output voltage.

　　Among them, after the digital comparator is configured, it can achieve fast response and protection against output voltage overvoltage or undervoltage; after the ADC15 is configured, it can accurately collect output voltage information, and then with the help of software design, it can also achieve output voltage fault protection.

　　4. References

　　1. UCD3138 datasheet, Texas Instruments Inc.

　　2. UCD31xx Fusion Digital Power Peripherals Programmer's Manual, Texas Instruments Inc.

　　3. UCD31xx Miscellaneous Analog Control _MAC_, Texas Instruments Inc.