Development and application of USB3.0 bus technology based on CYPRESS

1. Introduction

USB (Universal Serial Bus) has been widely used for its features such as no configuration required and plug-and-play. The USB2.0 standard proposed in 2004 has a maximum transmission speed of 480Mbps. However, in the USB3.0 standard, its maximum transmission speed is almost 10 times that of the traditional USB2.0 transmission speed, reaching 5.0Gbps, and is defined as an "ultra-high-speed USB interface". This paper studies and develops the USB3.0 bus based on the FX3 series USB3.0 chip of CYPRESS.

2.USB3.0 interface chip overview

Cypress's EZ-USB FX3 is a new generation of USB3.0 peripheral controller with highly integrated and flexible features, allowing system designers to add USB3.0 to any system. This article uses the FX3 series USB3.0 chip CYUSB3014.

FX3 is fully compatible with USB3.0 V1.0 and USB2.0 specifications. The integrated USB2.0 OTG controller allows the chip to be used as a master or slave device. In addition, it also supports some commonly used peripheral interfaces such as SPI, I2C, UART and I2S to communicate with external devices.

FX3 has a fully configurable parallel general programmable interface GPIF II, which can be connected to any processor, ASIC or FPGA. It can be easily and seamlessly connected to a variety of commonly used interfaces, such as asynchronous SRAM, asynchronous and synchronous address data multiplexing interface, parallel ATA, etc. EZ-USB FX3 integrates USB3.0 and USB2.0 physical layer (PHY) and 32-bit ARM926EJ-S microprocessor, has powerful data processing capabilities, and can be used to build customized applications.

3. Overall system design

This system design is mainly composed of software and hardware. The software part mainly includes three parts: PC application, FX3 firmware program, and FPGA program. The hardware part is mainly composed of FPGA, USB3.0 chip and DDR2. The system block diagram of the hardware is shown in Figure 2. This paper mainly completes the design of hardware, PC application and FPGA program.

The FX3 firmware program uses the firmware program of the Cypress SDK development kit.

3.1 DDR module design

Compared with FPGA, USB3.0 interface is a high-speed receiving unit. Data cache is an indispensable part between systems with different working speeds. Generally speaking, the use of FIFO can basically make each system work at its own clock frequency, and data can be exchanged without repeated handshake signals. The data designed in this article is stored on the computer. Since the hardware configuration of each computer may be different, we designed a DDR2 virtual FIFO module to cache data, which can provide sufficient cache for batch transmission, without worrying about data loss caused by insufficient cache and insufficient access to data by the computer.

This system uses two MT47H64M16HR chips, two DDR chips in parallel control bus and address bus, the total storage capacity reaches 2Gbit, the read and write width is 16bit, it has abundant resources, enough to meet the needs of this system.

3.2 USB3.0 interface design

Unlike USB2.0, when USB3.0 communicates with a computer, it has its own dedicated data path, dedicated data transmission line and independent data reception line, namely the four-wire differential signal SSRX+/- and SSTX+/- in Figure 3, so that full-duplex can be truly realized. At the same time, USB3.0 is also compatible with the D+/- signal interface of USB2.0, so it can be seamlessly connected with USB2.0. Using the slave device FIFO interface to link with FPGA, the transmission speed can reach 320MBps. Figure 3 shows the circuit connection between the USB chip, FPGA and PC.

3.3 FPGA Logic Design

FPGA is the core of the whole system. It needs to generate test data and store it in DDR2, as well as transfer the data read from DDR2 to the large internal FIFO of CYUSB3014. Therefore, it is mainly composed of the modules shown in Figure 2.

3.3.1 USB interface module

The USB interface module mainly processes read and write commands. Read and write commands require the computer to control the transmission through USB and pass them to CYUSB3014, which then converts the specific commands into level signals and sends them to the IO port of the FPGA. The USB interface module determines whether it is a read command or a write command based on the level signal on UART_RX, and finally generates valid signals such as chip select CS, enable OE, read/write control, etc. of CYUSB3014.

When it is a write command, CYUSB3014 needs to send out the data read from DDR2; when it is a read command, read the data passed by CYUSB3014. The flow chart is shown in Figure 4.

3.3.2 Test Data Module

When the computer sends a read command to the FPGA, the FPGA generates test data. The 32-bit data has the upper 16 bits as 0 and the lower 16 bits as a cyclic count. After a cycle is sent, it is automatically cleared.

The maximum packet size for bulk transmission is 1024 bytes, so the test data changes cyclically between 0 and 255.

After the test data is generated, the data transmission process is DATA->

DDR2->FIFO->CYUSB3014->PC, realizing the function of uploading test data to PC.

3.3.3 DDR2 Interface Module

This part is directly responsible for the peripheral DDR2 interface, which is implemented using the FPGA's DDRII SDRAM IP core. The timing parameters of the controller are set according to the DDR2 chip MT47H64M16HR. The controller generates an interface that meets the MT47H64M16HR timing based on these parameter values, and then the DDR2 module performs read and write control.

4. Test results and analysis

4.1 Write data test

When the application sends a write command to the USB, the FPGA generates test data and passes it to FX3 for upload to the PC.

1000MB of data was collected and recorded for analysis in MATLAB.

The CYPRESS official development package comes with streamer software for speed testing. Select Bulk in endpoint in the Endpoint option (Bulk Out corresponds to the PC writing data to the FPGA). Since the maximum packet during bulk transmission is 1024 bytes, it is necessary to set Packets perXfer to 256 or less and Xfers to Queue to 4. The speed test results will be different for different USB3.0 controllers. Figure 7 shows the test and analysis results under the 64-bit WIN7 system. As shown in Figure 7(a), after a period of speed testing, 23704 successful packets and 0 failed packets, the speed of writing data to the PC can reach 178800KB/S, that is, 1.43Gbps. In order to verify the correctness of the data, the collected 8.0Gb data is analyzed in MATLAB. Since the test data changes cyclically between 0 and 255, the correctness of the data can be judged based on whether the data difference of each packet of data is 1. If it is not 1, an error is reported.

As shown in FIG7( b ), the read data is correct, and no data loss or error occurs.

4.2 Reading data test

Similarly, when the application sends a read command to the USB, a set of regular test data is generated and sent to CYUSB3014, and the FPGA reads the data directly. The following Figure 8(a) shows the read speed test result, 18252 successful packets, 0 failures, and the speed of writing data to the USB can reach 179000KB/S, that is, 1.432Gbps. The randomly collected 32k data is recorded in the FPGA and analyzed. Similarly, the correctness of the data can be judged based on the difference between the data. As shown in Figure 8(b), the written data is correct, and there is no loss or error in the data.

5. Conclusion

This paper develops and applies USB3.0 based on FPGA and CYUSB3014. In view of the system architecture of this paper, although the test data are all generated inside the FPGA, it has great reference significance for the data acquisition system that actually uses high sampling rate AD.